參數(shù)資料
型號(hào)： ADUC7023BCPZ62I-RL
廠商： Analog Devices Inc
文件頁數(shù)： 51/96頁
文件大?。?/td> 0K
描述： IC MCU 12BIT 62KB FLASH 32LFCSP
標(biāo)準(zhǔn)包裝： 5,000
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 44MHz
連通性： I²C，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 12
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2K x 32
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
Data Sheet
ADuC7023
| Page 55 of 96
Table 63. SPISTA MMR Bit Designations
Bit
Name
Description
15 to 12
Reserved bits.
11
SPIREX
SPI Rx FIFO excess bytes present.
This bit is set when there are more bytes in the Rx FIFO than indicated in the SPIMDE bits in SPICON
This bit is cleared when the number of bytes in the FIFO is equal or less than the number in SPIMDE.
10 to 8
SPIRXFSTA[2:0]
SPI Rx FIFO status bits.
[000] = Rx FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
7
SPIFOF
SPI Rx FIFO overflow status bit.
This bit is set when the Rx FIFO is full when new data is loaded to the FIFO. This bit generates an interrupt
except when SPIRFLH is set in SPICON.
This bit is cleared when the SPISTA register is read.
6
SPIRXIRQ
SPI Rx IRQ status bit.
This bit is set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the
required number of bytes have been received.
This bit is cleared when the SPISTA register is read.
5
SPITXIRQ
SPI Tx IRQ status bit.
This bit is set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required
number of bytes have been transmitted.
This bit is cleared when the SPISTA register is read.
4
SPITXUF
SPI Tx FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt
except when SPITFLH is set in SPICON.
This bit is cleared when the SPISTA register is read.
3 to 1
SPITXFSTA[2:0]
SPI Tx FIFO status bits.
[000] = Tx FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid byte in the FIFO.
[011] = 3 valid byte in the FIFO.
[100] = 4 valid byte in the FIFO.
0
SPIISTA
SPI interrupt status bit.
This bit is set to 1 when an SPI based interrupt occurs.
This bit is cleared after reading SPISTA.
SPIRX Register
Name:
SPIRX
Address:
0xFFFF0A04
Default value: 0x00
Access:
Read
Function:
This 8-bit MMR is the SPI receive register.
SPITX Register
Name:
SPITX
Address:
0xFFFF0A08
Default value: 0xXX
Access:
Write
Function:
This 8-bit MMR is the SPI transmit register.
Rev. E
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