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參數(shù)資料
| 型號： | ADUC7023BCPZ62I-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 62KB FLASH 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | I²C，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7023
Data Sheet
| Page 42 of 96
REMAP Register
Name:
REMAP
Address:
0xFFFF0220
Default value:
0x00
Access:
Read/write
Table 36. REMAP MMR Bit Designations
Bit
Name
Description
7 to 5
Reserved.
4
Read-only bit. Indicates the size of the
Flash/EE memory available. If this bit is set,
only 32 kB of Flash/EE memory is available.
3
Read-only bit. Indicates the size of the
SRAM memory available. If this bit is set,
only 4 kB of SRAM is available.
2 to 1
JTAFO
Read only bits. See the P0.0/BM
description for further details.
If = [00], then P0.1/P0.2/P0.3 are
configured as JTAG pins.
If = [1x], then P0.1/P0.2/P0.3 are
configured as GPIO pins.
These bits are configured by the kernel
after any reset sequence and depend on
the state of P0.0 during the last reset
sequence.
0
Remap
Remap bit.
This bit is set by the user to remap the
SRAM to Address 0x00000000.
This bit is cleared automatically after reset
to remap the Flash/EE memory to Address
0x00000000.
Reset Operation
There are four kinds of reset: external, power-on, watchdog
expiration, and software force. The RSTSTA register indicates
the source of the last reset, and RSTCLR allows clearing of the
RSTSTA register. These registers can be used during a reset
exception service routine to identify the source of the reset. If
RSTSTA is null, the reset is external.
The RSTCFG register allows different peripherals to retain their
state after a watchdog or software reset.
RSTSTA Register
Name:
RSTSTA
Address:
0xFFFF0230
Default value: 0x01
Access:
Read/write
Table 37. RSTSTA MMR Bit Designations
Bit
Description
7 to 3
Reserved.
2
Software reset.
This bit is set by the user to force a software reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.
1
Watchdog timeout.
This bit is set automatically when a watchdog
timeout occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
0
Power-on reset.
This bit is set automatically when a power-on reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
RSTCLR Register
Name:
RSTCLR
Address:
0xFFFF0234
Default value: 0x00
Access:
Write
Function:
Note that to clear the RSTSTA register, users
must write the Value 0x07 to the RSTCLR
register.
RSTCFG Register
Name:
RSTCFG
Address:
0xFFFF024C
Default value: 0x00
Access:
Read/write
Table 38. RSTCFG MMR Bit Designations
Bit
Description
7 to 3
Reserved. Always set to 0.
2
This bit is set to 1 to configure the DAC outputs to retain
their state after a watchdog or software reset.
This bit is cleared for the DAC pins and registers to
return to their default state.
1
Reserved. Always set to 0.
0
This bit is set to 1 to configure the GPIO pins to retain
their state after a watchdog or software reset.
This bit is cleared for the GPIO pins and registers to
return to their default state.
Rev. E
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