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參數(shù)資料
| 型號： | ADUC7023BCPZ62I-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 76/96頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 62KB FLASH 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | I²C，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7023
Data Sheet
| Page 78 of 96
FIQSTA
FIQSTA is a read-only register that provides the current enabled
FIQ source status (effectively a logic AND of the FIQSIG and
FIQEN bits). When set to 1, that source generates an active FIQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
FIQSTA Register
Name:
FIQSTA
Address:
0xFFFF0100
Default value: 0x00000000
Access:
Read only
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 89. This MMR allows the control of a
programmed source interrupt.
Table 89. SWICFG MMR Bit Designations
Bit
Description
31 to 3
Reserved.
2
Programmed interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
1
Programmed interrupt IRQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
0
Reserved.
Any interrupt signal must be active for at least the minimum
interrupt latency time, to be detected by the interrupt controller
and to be detected by the user in the IRQSTA and FIQSTA
registers.
08675-
035
POINTER TO
FUNCTION
(IRQVEC)
IRQ_SOURCE
FIQ_SOURCE
PROGRAMMABLE PRIORITY
PER INTERRUPT (IRQP0/IRQP1/IRQP2)
INTERNAL
ARBITER
LOGIC
INTERRUPT VECTOR
BIT 31 TO
BIT 23
UNUSED
BIT 1 TO
BIT 0
LBSs
BIT 22 TO BIT 7
(IRQBASE)
BIT 6 TO
BIT 2
HIGHEST
PRIORITY
ACTIVE IRQ
Figure 41. Interrupt Structure
VECTORED INTERRUPT CONTROLLER (VIC)
The ADuC7023 incorporates an enhanced interrupt control
system or vectored interrupt controller. The vectored interrupt
controller for IRQ interrupt sources is enabled by setting Bit 0
of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables
the vectored interrupt controller for the FIQ interrupt sources.
The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:
Vectored interrupts allow a user to define separate interrupt
service routine addresses for every interrupt source. This is
achieved by using the IRQBASE and IRQVEC registers.
IRQ/FIQ interrupts can be nested up to eight levels depending
on the priority settings. An FIQ still has a higher priority
than an IRQ. Therefore, if the VIC is enabled for both the
FIQ and IRQ and prioritization is maximized, then it is
possible to have 16 separate interrupt levels.
Programmable interrupt priorities, using the IRQP0 to IRQP2
registers, can be assigned an interrupt priority level value
between 0 and 7.
VIC MMRs
IRQBASE Register
The vector base register, IRQBASE, is used to point to the start
address of memory used to store 32 pointer addresses. These
pointer addresses are the addresses of the individual interrupt
service routines.
Name:
IRQBASE
Address:
0xFFFF0014
Default value: 0x00000000
Access:
Read and write
Table 90. IRQBASE MMR Bit Designations
Bit
Type
Initial Value
Description
31:16
Read only
Reserved
Always read as 0.
15:0
R/W
0
Vector base address.
Rev. E
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