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參數(shù)資料
| 型號(hào)： | ADUC7023BCPZ62I-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 61/96頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 12BIT 62KB FLASH 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | I²C，SPI |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 12 |
| 程序存儲(chǔ)器容量： | 64KB（32K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADuC7023
Data Sheet
| Page 64 of 96
Bit
Name
Description
4
I2CGCCLR
I2C general call status and ID clear bit.
Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register.
This bit is cleared at all other times.
3
I2CHGCEN
I2C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having
received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CxALT against
the receive register. If the contents match, the device has received a hardware general call. This is used if a
device needs urgent attention from a master device without knowing which master it needs to turn to. This is a
broadcast message to all master devices on the bus. The ADuC7023 watches for these addresses. The device
that requires attention embeds its own address into the message. All masters listen, and the one that can
handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be
written to 1, as per the I2C January 2000 bus specification.
This bit and I2CGCEN are set to enable hardware general call recognition in slave mode.
This bit is cleared to disable recognition of hardware general call commands.
2
I2CGCEN
I2C general call enable. This bit is set to enable the slave device to acknowledge an I2C general call, Address
0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of
the slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus
specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part
of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call.
The user must take corrective action by reprogramming the device address.
This bit is set to allow the slave acknowledge I2C general call commands.
This bit is cleared to disable recognition of general call commands.
1
ADR10EN
I2C 10-bit address mode.
This bit is set to 1 to enable 10-bit address mode.
This bit is cleared to 0 to enable normal address mode.
0
I2CSEN
I2C slave enable bit.
This bit is set by user to enable I2C slave mode.
This bit is cleared by the user to disable I2C slave mode.
I2C Slave Status Registers, I2CxSSTA
Name:
I2C0SSTA, I2C1SSTA
Address:
0xFFFF082C, 0xFFFF092C
Default value:
0x0000, 0x0000
Access:
Read/write
Function:
These 16-bit MMRs are the I2C status registers in slave mode.
Rev. E
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| ADUC7024BCPZ62 | 功能描述:IC MCU FLSH 62K ANLG I/O 64LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC7xxx 標(biāo)準(zhǔn)包裝:60 系列:PSOC® 3 CY8C38xx 核心處理器:8051 芯體尺寸:8-位 速度:67MHz 連通性:EBI/EMI，I²C，LIN，SPI，UART/USART 外圍設(shè)備:電容感應(yīng)，DMA，LCD，POR，PWM，WDT 輸入/輸出數(shù):25 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:2K x 8 RAM 容量:8K x 8 電壓 - 電源 (Vcc/Vdd):1.71 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 2x20b，D/A 4x8b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:48-VFQFN 裸露焊盤 包裝:托盤 |
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