參數(shù)資料
型號(hào)： ADSP-TS203SABP-X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： TigerSHARC Embedded Processor
中文描述： 32-BIT, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, EBGA-576
文件頁數(shù)： 9/40頁
文件大?。?/td> 609K
代理商： ADSP-TS203SABP-X
ADSP-TS203S
Preliminary Technical Data
Rev. PrB
|
Page 9 of 40
|
December 2003
Each link port has its own triple-buffered quad-word input and
double-buffered quad-word output registers. The DSP’s core
can write directly to a link port’s transmit register and read from
a receive register, or the DMA controller can perform DMA
transfers through four (two transmit and two receive) dedicated
link port DMA channels.
Each link port direction has three signals that control its opera-
tion. For the transmitter, LxCLKOUT is the output transmit
clock, LxACKI is the handshake input to control the data flow,
and the LxBCMPO output indicates that the block transfer is
complete. For the receiver, LxCLKIN is the input receive clock,
LxACKO is the handshake output to control the data flow, and
the LxBCMPI input indicates that the block transfer is com-
plete. The LxDATO3–0 pins are the data output bus for the
transmitter and the LxDATI3–0 pins are the input data bus for
the receiver.
The two link ports on the ADSP-TS203S processor differ from
the link ports on the ADSP-TS201. The ADSP-TS203S proces-
sor’s two link ports are restricted to operate at half-speed; the
SPD bits in LTCTLx registers permit divide by 2 and divide by 4
transfer speeds—the divide by 1 and divide by 1.5 values are ille-
gal for ADSP-TS203S processor. Because the L2 and L3 link
ports are not available on the ADSP-TS203S, there are a number
of pin out differences between the ADSP-TS203S processor and
the ADSP-TS201 processor.
Applications can program separate error detection mechanisms
for transmit and receive operations (applications can use the
checksum mechanism to implement consecutive link port
transfers), the size of data packets, and the speed at which bytes
are transmitted.
TIMER AND GENERAL-PURPOSE I/O
The ADSP-TS203S processor has a timer pin (TMR0E) that
generates output when a programmed timer counter has
expired and four programmable general-purpose I/O pins
(FLAG3–0) that can function as either single-bit input or out-
put. As outputs, these pins can signal peripheral devices; as
inputs, they can provide the test for conditional branching.
RESET AND BOOTING
The ADSP-TS203S processor has three levels of reset:
Power-up reset—After power-up of the system (SCLK, all
static inputs, and strap pins are stable), the RST_IN pin
must be asserted (low).
Normal reset—For any chip reset following the power-up
reset, the RST_IN pin must be asserted (low).
DSP-core reset—When setting the SWRST bit in
EMUCTL, the DSP core is reset, but not the external port
or I/O.
For normal operations, tie the RST_OUT pin to the POR_IN
pin.
After reset, the ADSP-TS203S processor has four boot options
for beginning operation:
Boot from EPROM.
Boot by an external master (host or another ADSP-TS203S
processor).
Boot by link port.
No boot—Start running from memory address selected
with one of the IRQ3–0 interrupt signals. See
Table 2
.
Using the ‘no boot’ option, the ADSP-TS203S processor must
start running from memory when one of the interrupts is
asserted.
The ADSP-TS203S processor core always exits from reset in the
idle state and waits for an interrupt. Some of the interrupts in
the interrupt vector table are initialized and enabled after reset.
For more information on boot options, see the
EE-200: ADSP-
TS20xS Boot Loader Kernels Operation
on the Analog Devices
website (
)
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