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參數資料
| 型號： | ADSP-TS203SABP-X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | TigerSHARC Embedded Processor |
| 中文描述： | 32-BIT, OTHER DSP, PBGA576 |
| 封裝： | 25 X 25 MM, MS-034, EBGA-576 |
| 文件頁數： | 6/40頁 |
| 文件大?。?/td> | 609K |
| 代理商： | ADSP-TS203SABP-X |
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Rev. PrB
|
Page 6 of 40
|
December 2003
ADSP-TS203S
Preliminary Technical Data
The external bus is configured for 32-bit, little-endian opera-
tions. Unlike the ADSP-TS201, the ADSP-TS203S processor’s
external port cannot support 64-bit operations; the external bus
width control bits (bits 21-19) must =0 in the SYSCON regis-
ter—all other values are illegal for the ADSP-TS203S processor.
Because the external port is restricted to 32 bits on the ADSP-
TS203S processor, there are a number of pin out differences
between the ADSP-TS203S processor and the ADSP-TS201
processor.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high-
order address lines to generate memory bank select signals.
The ADSP-TS203S processor provides programmable memory,
pipeline depth, and idle cycle for synchronous accesses, and
external acknowledge controls to support interfacing to pipe-
lined or slow devices, host processors, and other memory-
mapped peripherals with variable access, hold, and disable time
requirements.
Host Interface
The ADSP-TS203S processor provides an easy and configurable
interface between its external bus and host processors through
the external port. To accommodate a variety of host processors,
the host interface supports pipelined or slow protocols for
ADSP-TS203S processor accesses of the host as slave or pipe-
lined for host accesses of the ADSP-TS203S processor as slave.
Each protocol has programmable transmission parameters,
such as idle cycles, pipe depth, and internal wait cycles.
The host interface supports burst transactions initiated by a host
processor. After the host issues the starting address of the burst
and asserts the BRST signal, the DSP increments the address
internally while the host continues to assert BRST.
Figure 3. ADSP-TS203S Memory Map
RESERVED
RESERVED
INTERNAL REGISTERS (UREGS)
INTERNAL MEMORY BLOCK 4
INTERNAL MEMORY BLOCK 2
INTERNAL MEMORY BLOCK 0
0x03FFFFFF
0X001E0000
0x001E03FF
0x000C7FFF
0x000C0000
0x00087FFF
0x00080000
0x00047FFF
0x00040000
0x00007FFF
0x00000000
INTERNAL SPACE
PROCESSOR ID 7
PROCESSOR ID 6
PROCESSOR ID 5
PROCESSOR ID 4
PROCESSOR ID 3
PROCESSOR ID 2
PROCESSOR ID 1
PROCESSOR ID 0
BROADCAST
HOST (
MSH
)
BANK 1(
MS1
)
BANK 0(
MS0
)
MSSD BANK 0 (
MSSD0
)
INTERNAL MEMORY
0x50000000
0x40000000
0x38000000
0x30000000
0x2C000000
0x28000000
0x24000000
0x20000000
0x1C000000
0x18000000
0x14000000
0x10000000
0X0C000000
0x03FFFFFF
0x00000000
GLOBAL SPACE
0xFFFFFFFF
M
E
EACH IS A COPY
OF INTERNAL SPACE
RESERVED
INTERNAL MEMORY BLOCK 6
RESERVED
RESERVED
RESERVED
RESERVED
SOC REGISTERS (UREGS)
0X001F0000
0x001F03FF
MSSD BANK 1 (
MSSD1
)
MSSD BANK 2 (
MSSD2
)
MSSD BANK 3 (
MSSD3
)
0x60000000
0x70000000
0x80000000
RESERVED
RESERVED
RESERVED
RESERVED
0x54000000
0x44000000
0x64000000
0x74000000
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相關代理商/技術參數 |
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|---|---|
| ADSP-TS203SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-EX-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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