參數(shù)資料
型號: ADSP-TS203SABP-X
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: TigerSHARC Embedded Processor
中文描述: 32-BIT, OTHER DSP, PBGA576
封裝: 25 X 25 MM, MS-034, EBGA-576
文件頁數(shù): 20/40頁
文件大?。?/td> 609K
代理商: ADSP-TS203SABP-X
Rev. PrB
|
Page 20 of 40
|
December 2003
ADSP-TS203S
Preliminary Technical Data
When default configuration is used, no external resistor is
needed on the strap pins. To apply other configurations, a 500
resistor connected to V
DD_IO
is required. If providing external
pulldowns, do not strap these pins directly to V
SS
; the strap pins
require 500
resistor straps.
All strap pins are sampled on the rising edge of RST_IN (de-
assertion edge). Each pin latches the strapped pin state (state of
the strap pin at the rising edge of RST_IN). Shortly after de-
assertion of RST_IN, these pins are re-configured to their nor-
mal functionality.
These strap pins have an internal pull-down resistor, pull-up
resistor, or no-resistor (three-state) on each pin. The resistor
type, which is connected to the I/O pad, depends on whether
RST_IN is active (low) or if RST_IN is de-asserted (high).
Table 16
shows the resistors that are enabled during active reset
and during normal operation
SYS_REG_WE
I
(pd_0)
BUSLOCK
SYSCON and SDRCON Write Enable.
0 = one-time writable after reset (default)
1 = always writable
Test Mode 1. Do not overdrive default value during reset.
TM1
I
(pu)
I
(pu)
I
(pu)
L1BCMPO
TM2
TM2
Test Mode 2. Do not overdrive default value during reset.
TM3
TM3
Test Mode 3. Do not overdrive default value during reset.
Table 15. Pin Definitions—I/O Strap Pins (Continued)
Signal
Type (at
Reset)
On Pin…
Description
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Table 16. Strap Pin Internal Resistors—Active Reset
(RST_IN = 0) Versus Normal Operation (RST_IN = 1)
PIN
BMS
BM
TMR0E
BUSLOCK
L1BCMPO
TM2
TM3
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
=
internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP ID=0
RST_IN = 0
(pd_0)
(pd)
(pd)
(pd_0)
(pu)
(pu)
(pu)
RST_IN = 1
(pu_0)
Driven
Driven
(pu_0)
Driven
Driven
Driven
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