參數(shù)資料
型號(hào): ADSP-TS203SABP-X
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號(hào)處理
英文描述: TigerSHARC Embedded Processor
中文描述: 32-BIT, OTHER DSP, PBGA576
封裝: 25 X 25 MM, MS-034, EBGA-576
文件頁(yè)數(shù): 8/40頁(yè)
文件大?。?/td> 609K
代理商: ADSP-TS203SABP-X
Rev. PrB
|
Page 8 of 40
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December 2003
ADSP-TS203S
Preliminary Technical Data
external data bus; outputs addresses, memory selects
(MSSD3–0) and the IORD, IOWR, IOEN, and RD/WR
strobes; and responds to ACK.
DMA chaining. DMA chaining operations enable applica-
tions to automatically link one DMA transfer sequence to
another for continuous transmission. The sequences can
occur over different DMA channels and have different
transmission attributes.
Two-dimensional transfers. The DMA controller can
access and transfer two-dimensional memory arrays on any
DMA transmit or receive channel. These transfers are
implemented with index, count, and modify registers for
both the X and Y dimensions.
LINK PORTS (LVDS)
The DSP’s two full-duplex link ports each provide additional
four-bit receive and four-bit transmit I/O capability, using Low-
Voltage, Differential-Signal (LVDS) technology. With the abil-
ity to operate at a double data rate—latching data on both the
rising and falling edges of the clock—running at 250 MHz, each
link port can support up to 250M bytes per second per direc-
tion, for a combined maximum throughput of 1G bytes per
second.
The link ports provide an optional communications channel
that is useful in multiprocessor systems for implementing point-
to-point interprocessor communications. Applications can also
use the link ports for booting.
Figure 4. ADSP-TS203S Shared Memory Multiprocessing System
CLKS/REFS
ADDR31–0
DATA31–0
BR1
BR7–2,0
ADDR31–0
DATA31–0
BR0
BR7–1
BMS
CPA
CONTROL
ADSP-TS203S #0
CONTROL
ADSP-TS203S #1
ADSP-TS203S #7
ADSP-TS203S #6
ADSP-TS203S #5
ADSP-TS203S #4
ADSP-TS203S #3
ADSP-TS203S #2
RESET
RST_IN
CLKS/REFS
RST_OUT
ID2–0
SCLK_V
REF
V
REF
SCLKRAT2–0
SCLK
000
CLOCK
REFERENCE
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
CS
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
WE
ADDR
DATA
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
RD
MS1–0
ACK
ID2–0
RST_IN
001
HBG
MSH
HBR
BOFF
BRST
WRL
C
A
D
C
A
D
SDRAM
MEMORY
(OPTIONAL)
MSSD3–0
IORD
IOWR
IOEN
RAS
CAS
LDQM
SDWE
SDCKE
SDA10
CS
RAS
CAS
DQM
WE
CKE
A10
ADDR
DATA
CLK
DMAR3–0
DPA
LINK
DEVICES
(2 MAX)
(OPTIONAL)
LxCLKINP/N
LxACKO
LxBCMPI
LxDATI3–0P/N
LxBCMPO
LxDATO3–0P/N
LxCLKOUTP/N
LxACKI
TMR0E
BM
CONTROLIMP1–0
DS2–0
LINK
IRQ3–0
FLAG3–0
LINK
BUSLOCK
CLOCK
JTAG
POR_IN
REFERENCE
LINK
DEVICES
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