參數(shù)資料
型號： ADSP-TS203SABP-X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： TigerSHARC Embedded Processor
中文描述： 32-BIT, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, EBGA-576
文件頁數(shù)： 28/40頁
文件大?。?/td> 609K
代理商： ADSP-TS203SABP-X
Rev. PrB
|
Page 28 of 40
|
December 2003
ADSP-TS203S
Preliminary Technical Data
Link Port—Data Out Timing
Table 25
with
Figure 14
,
Figure 15
,
Figure 16
,
Figure 17
,
Figure 18
, and
Figure 19
provide the data out timing for the
LVDS link ports.
Table 25. Link Port—Data Out Timing
Parameter
Outputs
t
REO
t
FEO
t
LCLKOP
Min
Max
Units
Rising Edge (
Figure 14
)
Falling Edge (
Figure 14
)
LxCLKOUT Period (
Figure 15
)
200
200
1.1
×
LCR
×
t
CCLK1,2
ps
ps
ns
greater of 2.0 or
0.9
×
LCR
×
t
CCLK1,2
0.4
×
t
LCLKOP1
0.4
×
t
LCLKOP1
t
LCLKOH
t
LCLKOL
t
COJT
t
LDOS
LxCLKOUT High (
Figure 15
LxCLKOUT Low (
Figure 15
)
LxCLKOUT Jitter (
Figure 15
)
LxDATO Output Setup, LCR = 1 and LCR = 1.5 (
Figure 16
) smaller of 2.5
3
or
0.6
×
t
LCLKOP1
0.6
×
t
LCLKOP1
–/+70
ns
ns
ps
ns
0.25
×
LCR
×
t
CCLK
– 0.15
1,2,4
smaller of 2.5
3
or
0.25
×
LCR
×
t
CCLK
– 0.3
1,2,4
LxDATO Output Setup, LCR = 2 and LCR = 4 (
Figure 16
)
ns
t
LDOH
LxDATO Output Hold, LCR = 1 and LCR = 1.5 (
Figure 16
) 0.25
×
LCR
×
t
CCLK
– 0.15
1,2,4
LxDATO Output Hold, LCR = 2 and LCR = 4 (
Figure 16
)
Delay from LxACKI rising edge to first transmission clock
edge (
Figure 17
)
LxBCMPO Valid (
Figure 17
)
LxBCMPO Hold (
Figure 18
).
ns
ns
ns
0.25
×
LCR
×
t
CCLK
– 0.3
1,2,4
t
LACKID
14
×
LCR
×
t
CCLK1,2
t
BCMPOV
t
BCMPOH
Inputs
t
LACKIS
2
×
LCR
×
t
CCLK1,2
ns
ns
3
×
TSW - 0.5
1,,5
LxACKI low setup to guarantee that the transmitter stops
transmitting (
Figure 18
).
LxACKI high setup to guarantee that the transmitter
continues its transmission without any interruption
(
Figure 19
).
LxACKI high hold time (
Figure 18
).
14
×
LCR
×
t
CCLK1,2
ns
t
LACKIH
0.5
1
ns
1
Timing is relative to the 0 differential voltage (V
OD
= 0)
2
LCR (Link port Clock Ratio) = 1, 1.5, 2 or 4. t
CCLK
is the core period
3
The 2.5 value for t
LDOS
applies for LCLKOUT
≤
100 MHz.
4
t
LDOS
and t
LDOH
values include LCLKOUT jitter.
5
TSW is a short-word transmission period. For a 4-Bit Link it is 2
×
LCR
×
t
CCLK
and for a 1-Bit Link is 8
×
LCR
×
t
CCLK
ns
Figure 14. Link Ports—Differential Output Signals Transition Time
+
|
VOD
|
MIN
VOD= 0V
–
|
VOD
|
MIN
t
REO
t
FEO
VO_N
VO_P
RL
CL
CL_P
CL_N
RL= 100
CL= 0.1pF
CL_P= 5pF
CL_N= 5pF
Figure 15. Link Ports—Output Clock
LxCLKOUT
VOD= 0V
t
COJT
t
LCLKOL
t
LCLKOH
t
LCLKOP
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