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參數(shù)資料
| 型號： | ADSP-TS203SABP-X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | TigerSHARC Embedded Processor |
| 中文描述： | 32-BIT, OTHER DSP, PBGA576 |
| 封裝： | 25 X 25 MM, MS-034, EBGA-576 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大?。?/td> | 609K |
| 代理商： | ADSP-TS203SABP-X |
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ADSP-TS203S
Preliminary Technical Data
Rev. PrB
|
Page 7 of 40
|
December 2003
The host interface provides a deadlock recovery mechanism that
enables a host to recover from deadlock situations involving the
DSP. The BOFF signal provides the deadlock recovery mecha-
nism. When the host asserts BOFF, the DSP backs off the
current transaction and asserts HBG and relinquishes the exter-
nal bus.
The host can directly read or write the internal memory of the
ADSP-TS203S processor, and it can access most of the DSP reg-
isters, including DMA control (TCB) registers. Vector
interrupts support efficient execution of host commands.
Multiprocessor Interface
The ADSP-TS203S processor offers powerful features tailored
to multiprocessing DSP systems through the external port and
link ports. This multiprocessing capability provides highest
bandwidth for interprocessor communication, including:
Up to eight DSPs on a common bus
On-chip arbitration for glueless multiprocessing
Link ports for point to point communication
The external port and link ports provide integrated, glueless
multiprocessing support.
The external port supports a unified address space (see
Figure 3
)
that enables direct interprocessor accesses of each ADSP-
TS203S processor’s internal memory and registers. The DSP’s
on-chip distributed bus arbitration logic provides simple, glue-
less connection for systems containing up to eight ADSP-
TS203S processors and a host processor. Bus arbitration has a
rotating priority. Bus lock supports indivisible read-modify-
write sequences for semaphores. A bus fairness feature prevents
one DSP from holding the external bus too long.
The DSP’s two link ports provide a second path for interproces-
sor communications with throughput of 1G bytes per second.
The cluster bus provides 500M bytes per second throughput—
with a total of 1.5G bytes per second interprocessor bandwidth.
SDRAM Controller
The SDRAM controller controls the ADSP-TS203S processor’s
transfers of data to and from external synchronous DRAM
(SDRAM) at a throughput of 32 bits per SCLK cycle using the
external port and SDRAM control pins.
The SDRAM interface provides a glueless interface with stan-
dard SDRAMs—16M bit, 64M bit, 128M bit, and 256M bit. The
DSP supports directly a maximum of four banks of
64M words
×
32 bit of SDRAM. The SDRAM interface is
mapped in external memory in each DSP’s unified memory
map.
EPROM Interface
The ADSP-TS203S processor can be configured to boot from an
external 8-bit EPROM at reset through the external port. An
automatic process (which follows reset) loads a program from
the EPROM into internal memory. This process uses sixteen
wait cycles for each read access. During booting, the BMS pin
functions as the EPROM chip select signal. The EPROM boot
procedure uses DMA channel 0, which packs the bytes into 32-
bit instructions. Applications can also access the EPROM (write
flash memories) during normal operation through DMA.
The EPROM or Flash Memory interface is not mapped in the
DSP’s unified memory map. It is a byte address space limited to
a maximum of 16M bytes (twenty-four address bits). The
EPROM or Flash Memory interface can be used after boot via a
DMA.
DMA CONTROLLER
The ADSP-TS203S processor’s on-chip DMA controller, with
10 DMA channels, provides zero-overhead data transfers with-
out processor intervention. The DMA controller operates
independently and invisibly to the DSP’s core, enabling DMA
operations to occur while the DSP’s core continues to execute
program instructions.
The DMA controller performs DMA transfers between internal
memory and external memory and memory-mapped peripher-
als, the internal memory of other DSPs on a common bus, a host
processor, or link port I/O; between external memory and exter-
nal peripherals or link port I/O; and between an external bus
master and internal memory or link port I/O. The DMA con-
troller performs the following DMA operations:
External port block transfers. Four dedicated bidirectional
DMA channels transfer blocks of data between the DSP’s
internal memory and any external memory or memory-
mapped peripheral on the external bus. These transfers
support master mode and handshake mode protocols.
Link port transfers. Four dedicated DMA channels (two
transmit and two receive) transfer quad-word data only
between link ports and between a link port and internal or
external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the two
receive channels.
AutoDMA transfers. Two dedicated unidirectional DMA
channels transfer data received from an external bus master
to internal memory or to link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.
The DMA controller provides these additional features:
Flyby transfers. Flyby operations only occur through the
external port (DMA channel 0) and do not involve the
DSP’s core. The DMA controller acts as a conduit to trans-
fer data from an external I/O device to external SDRAM
memory. During a transaction, the DSP relinquishes the
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| ADSP-TS203SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-EX-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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