參數(shù)資料
型號： ADSP-TS203SABP-X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： TigerSHARC Embedded Processor
中文描述： 32-BIT, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, EBGA-576
文件頁數(shù)： 19/40頁
文件大?。?/td> 609K
代理商： ADSP-TS203SABP-X
ADSP-TS203S
Preliminary Technical Data
Rev. PrB
|
Page 19 of 40
|
December 2003
STRAP PIN FUNCTION DESCRIPTIONS
Some pins have alternate functions at reset. Strap options set
DSP operating modes. During reset, the DSP samples the strap
option pins. Strap pins have an internal pullup or pulldown for
the default value. If a strap pin is not connected to an overdriv-
ing external pullup, pulldown, or logic load, the DSP samples
the default value during reset. If strap pins are connected to
logic inputs, a stronger external pullup or pulldown may be
required to ensure default value depending on leakage and/or
low level input current of the logic load. To set a mode other
than the default mode, connect the strap pin to a sufficiently
stronger external pullup or pulldown.
Table 15
lists and
describes each of the DSP’s strap pins.
Table 14. Pin Definitions—Power, Ground, and Reference
Signal
V
DD
V
DD_A
V
DD_IO
V
DD_DRAM
V
REF
Type
P
P
P
P
I
Term
au
au
au
au
au
Description
V
DD
pins for internal logic.
V
DD
pins for analog circuits. Pay critical attention to bypassing this supply.
V
DD
pins for I/O buffers.
V
DD
pins for internal DRAM.
Reference voltage defines the trip point for all input buffers, except SCLK, RST_IN,
POR_IN, IRQ3–0, FLAG3–0, DMAR3–0, ID2–0, CONTROLIMP1–0, LxDATO3–0P/N,
LxCLKOUTP/N, LxDATI3–0P/N, LxCLKINP/N, TCK, TDI, TMS, and TRST. V
REF
can be
connected to a power supply or set by a voltage divider circuit as shown in
Figure 6
.
For more information, see Filtering Reference Voltage and Clocks on page 10.
System Clock Reference. Connect this pin to a reference voltage as shown in
Figure 7
.
For more information, see Filtering Reference Voltage and Clocks on page 10.
Ground pins.
No Connect. Do not connect these pins to anything (not to any supply, signal, or each
other). These pins are reserved and must be left unconnected.
SCLK_V
REF
I
1
au
V
SS
NC
G
—
au
nc
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
1
For more information on SCLK and SCLK_V
REF
on revision 0.0 silicon, see the
EE-179: ADSP-TS20xS TigerSHARC System Design Guidelines
on the Analog Devices website
www.analog.com
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