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參數(shù)資料
| 型號： | ADSP-TS203SABP-X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | TigerSHARC Embedded Processor |
| 中文描述： | 32-BIT, OTHER DSP, PBGA576 |
| 封裝： | 25 X 25 MM, MS-034, EBGA-576 |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 609K |
| 代理商： | ADSP-TS203SABP-X |
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Rev. PrB
|
Page 26 of 40
|
December 2003
ADSP-TS203S
Preliminary Technical Data
ENEDREG
6
STRAP SYS
7,8
JTAG SYS
9
Static pins – must be connected to V
SS
Strap pins
JTAG system pins
—
1.5
1.5
—
0.5
0.5
—
—
4.0
—
—
1.0
—
—
—
—
—
—
—
SCLK
TCK
1
The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus contention. The
apparent driver overlap, due to output disables being larger than output enables, is not actual.
2
For input specifications on FLAG3–0 pins, see
Table 17
.
3
These input pins are asynchronous and therefore do not need to be synchronized to a clock reference.
4
For additional requirement details, see
Reset and Booting on page 9
.
5
Reference clock depends on function.
6
These pins may change only during reset; recommend connecting it to V
DD_IO
/V
SS
.
7
STRAP pins include: BMS, BM, BUSLOCK, TMR0E, L1BCMPO, TM2, and TM3.
8
Specifications applicable during reset only.
9
JTAG system pins include: RST_IN, RST_OUT, POR_IN, IRQ3-0, DMAR3-0, HBR, BOFF, MS1-0, MSH, SDCKE, LDQM, BMS, IOWR, IORD, BM, EMU, SDA10, IOEN,
BUSLOCK, TMR0E, DATA31-0, ADDR31-0, RD, WRL, BRST, MSSD3-0, RAS, CAS, SDWE, HBG, BR7-0, FLAG3-0, L0DATOP3-0, L0DATON3-0, L1DATOP3-0,
L1DATON3-0, L0CLKOUTP, L0CLKOUTN, L1CLKOUTP, L1CLKOUTN, L0ACKI, L1ACKI, L0DATIP3-0, L0DATIN3-0, L1DATIP3-0, L1DATIN3-0, L0CLKINP,
L0CLKINN, L1CLKINP, L1CLKINN, L0ACKO, L1ACKO, ACK, CPA, DPA, L0BCMPO, L1BCMPO, L0BCMPI, L1BCMPI, ID2-0, CTRL_IMPD1-0, SCLKRAT2-0, DS2-
0, ENEDREG, TM2, TM3, TM4.
Figure 11. General AC Parameters Timing
Table 22. AC Signal Specifications (Continued)
(all values in this table are in nanoseconds)
Name
Description
I
(
I
(
O
(
O
(
O
(
1
O
(
1
R
REFERENCE
CLOCK
INPUT
SIGNAL
OUTPUT
SIGNAL
THREE-
STATE
OUTPUT
VALID
OUTPUT
HOLD
OUTPUT
ENABLE
OUTPUT
DISABLE
INPUT
HOLD
INPUT
SETUP
1.25V
1.25V
1.25V
t
SCLK
OR
t
TCK
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| ADSP-TS203SABPZ050 | 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-TS203SBBPZ050 | 制造商:Analog Devices 功能描述:DSP - Bulk |
| ADSQ-1410 | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
| ADSQ-1410-EX-C | 制造商:MURATA-PS 制造商全稱:Murata Power Solutions Inc. 功能描述:Quad 14-Bit, 10 MSPS Sampling A/D Converter |
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