- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375266 > ADSP-21060LC (Analog Devices, Inc.) DSP Microcomputer(DSP 微計(jì)算機(jī)) PDF資料下載
參數(shù)資料
| 型號(hào)： | ADSP-21060LC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DSP Microcomputer(DSP 微計(jì)算機(jī)) |
| 中文描述： | 微機(jī)的DSP（數(shù)字信號(hào)處理器微計(jì)算機(jī)） |
| 文件頁數(shù)： | 9/48頁 |
| 文件大?。?/td> | 515K |
| 代理商： | ADSP-21060LC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當(dāng)前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁
ADSP-21060C/ADSP-21060LC
–9–
REV. PrA
PRELIMINARY
output.
Multiprocessing ID
. Determines which multiprocessing bus request (
BR1
–
BR6
) is used by ADSP-
2106x. ID = 001 corresponds to
BR1
, ID = 010 corresponds to
BR2
, etc. ID = 000 in single-processor
systems. T hese lines are a system configuration selection which should be hardwired or only changed
at reset.
Rotating Priority Bus Arbitration Select
. When RPBA is high, rotating priority for multiprocessor
bus arbitration is selected. When RPBA is low, fixed priority is selected. T his signal is a system con-
figuration selection which must be set to the same value on every ADSP-2106x. If the value of RPBA is
changed during system operation, it must be changed in the same CLK IN cycle on every ADSP-2106x.
Core Priority Access
. Asserting its
CPA
pin allows the core processor of an ADSP-2106x bus slave
to interrupt background DMA transfers and gain access to the external bus.
CPA
is an open drain
output that is connected to all ADSP-2106xs in the system. T he
CPA
pin has an internal 5 k
pull-up
resistor. If core access priority is not required in a system, the
CPA
pin should be left unconnected.
Data T ransmit
(Serial Ports 0, 1). Each DT pin has a 50 k
internal pull-up resistor.
Data Receive
(Serial Ports 0, 1). Each DR pin has a 50 k
internal pull-up resistor.
T ransmit Clock
(Serial Ports 0, 1). Each T CLK pin has a 50 k
internal pull-up resistor.
Receive Clock
(Serial Ports 0, 1). Each RCLK pin has a 50 k
internal pull-up resistor.
TECHNICAL
should be pulled high; the processor’s own
BR
x line must not be pulled high or low because it is an
Pin
T ype
Function
SBTS
I/S
Suspend Bus Three-State
. External devices can assert
SBTS
(low) to place the external bus address,
data, selects and strobes in a high impedance state for the following cycle. If the ADSP-2106x
attempts to access external memory while
SBTS
is asserted, the processor will halt and the memory
access will not be completed until
SBTS
is deasserted.
SBTS
should only be used to recover from host
processor/ADSP-2106x deadlock, or used with a DRAM controller.
Interrupt Request Lines
. May be either edge-triggered or level-sensitive.
Flag Pins
. Each is configured via control bits as either an input or output. As an input, it can be
tested as a condition. As an output, it can be used to signal external peripherals.
T imer E xpired
. Asserted for four cycles when the timer is enabled and T COUNT decrements to
zero.
Host Bus Request
. Must be asserted by a host processor to request control of the ADSP-2106x’s
external bus. When
HBR
is asserted in a multiprocessing system, the ADSP-2106x that is bus master
will relinquish the bus and assert
HBG
. T o relinquish the bus, the ADSP-2106x places the address,
data, select and strobe lines in a high impedance state.
HBR
has priority over all ADSP-2106x bus
requests (
BR
6-1
) in a multiprocessing system.
control of the external bus.
HBG
is asserted (held low) by the ADSP-2106x until
HBR
is released. In a
multiprocessing system,
HBG
is output by the ADSP-2106x bus master and is monitored by all others.
Chip Select
. Asserted by host processor to select the ADSP-2106x.
Host Bus Acknowledge
. T he ADSP-2106x deasserts REDY (low) to add wait states to an asynchro-
nous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can
be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be
output if the
CS
and
HBR
inputs are asserted.
DMA Request 1
(DMA Channel 7).
DMA Request 2
(DMA Channel 8).
DMA Grant 1
(DMA Channel 7).
DMA Grant 2
(DMA Channel 8).
Multiprocessing Bus Requests
. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-
ship. An ADSP-2106x only drives its own
BR
x line (corresponding to the value of its ID
2-0
inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused
BR
x pins
IRQ
2-0
FLAG
3-0
I/A
I/O/A
T IMEX P
O
HBR
I/A
HBG
I/O
CS
REDY (O/D) O
I/A
DMAR1
DMAR2
DMAG1
DMAG2
BR
6-1
I/A
I/A
O/T
O/T
I/O/S
ID
2-0
I
RPBA
I/S
CPA
(O/D)
I/O
DT x
DRx
T CLK x
RCLK x
O
I
I/O
I/O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21060C | DSP Microcomputer(DSP 微計(jì)算機(jī)) |
| ADSP-21261 | SHARC Embedded Processor |
| ADSP-21261SKBC-150 | SHARC Embedded Processor |
| ADSP-21261SKBCZ150 | SHARC Embedded Processor |
| ADSP-21261SKSTZ150 | SHARC Embedded Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21060LCB-133 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21060LCBZ-133 | 功能描述:IC DSP CONTROLLER 32BIT 225PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21060LCW-133 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 33MHz 33MIPS 240-Pin CQFP 制造商:Rochester Electronics LLC 功能描述:SHARC IND.,3V,33MHZ CQFP HEAT SLUG DOWN - Bulk |
| ADSP-21060LCW-160 | 功能描述:IC DSP CONTROLLER 32BIT 240CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21060LCWZ-133 | 制造商:Analog Devices 功能描述:SHARC INDUSTRIAL 5V CQFP HEAT SLUG UP - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。