參數(shù)資料
型號: ADSP-21060LC
廠商: Analog Devices, Inc.
英文描述: DSP Microcomputer(DSP 微計算機)
中文描述: 微機的DSP(數(shù)字信號處理器微計算機)
文件頁數(shù): 14/48頁
文件大?。?/td> 515K
代理商: ADSP-21060LC
–14–
ADSP-21060C/ADSP-21060LC
REV. PrA
PRELIMINARY
DATA
TECHNICAL
POWE R DISSIPAT ION ADSP-21060C (5 V)
T hese specifications apply to the internal power portion of V
DD
only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
Operation
Peak Activity (I
DDINPE AK
)
Multifunction
High Activity (I
DDINHIGH
)
Multifunction
Low Activity (I
DDINLOW
)
Single Function
Instruction T ype
Instruction Fetch
Cache
Internal Memory
Internal Memory
Core Memory Access
2 per Cycle (DM and PM)
1 per Cycle (DM)
None
Internal Memory DMA
1 per Cycle
1 per 2 Cycles
1 per 2 Cycles
T o estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%
PEAK
×
I
DDINPEAK
+ %HIGH
×
I
DDINHIGH
+ %LOW
×
I
DDINLOW
+ %IDLE
×
I
DDIDLE
= power consumption
Parameter
Units
I
DDINPEAK
Supply Current (Internal)
1
t
CK
= 30 ns, V
DD
= max,
t
CK
= 25 ns, V
DD
= max,
745
850
mA
mA
I
DDINHIGH
Supply Current (Internal)
2
t
CK
= 30 ns, V
DD
= max,
t
CK
= 25 ns, V
DD
= max,
575
670
mA
mA
I
DDINLOW
Supply Current (Internal)
2
t
CK
= 30 ns, V
DD
= max,
t
CK
= 25 ns, V
DD
= max,
340
390
mA
mA
I
DDIDLE
Supply Current (Idle)
3
V
DD
= max
200
mA
NOT ES
S
1
T he test program used to measure I
represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2
I
is a composite average based on a range of high activity code. I
DDINLOW
is a composite average based on a range of low activity code.
3
Idle denotes ADSP-21060LC state during execution of IDLE instruction.
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