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參數(shù)資料
| 型號： | ADSP-21060LC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DSP Microcomputer(DSP 微計算機) |
| 中文描述： | 微機的DSP（數(shù)字信號處理器微計算機） |
| 文件頁數(shù)： | 8/48頁 |
| 文件大?。?/td> | 515K |
| 代理商： | ADSP-21060LC |
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–8–
ADSP-21060C/ADSP-21060LC
REV. PrA
PRELIMINARY
the ADSP-2106x’s internal memory. In a multiprocessing system
WR
is output by the bus master and
is input by all other ADSP-2106xs.
DRAM Page Boundary
. T he ADSP-2106x asserts this pin to signal that an external DRAM page
boundary has been crossed. DRAM page size must be defined in the ADSP-2106x’s memory control
register (WAIT ). DRAM can only be implemented in external memory Bank 0; the PAGE signal can
only be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.
Clock Output Reference
. In a multiprocessing system ADRCLK is output by the bus master.
Synchronous Write Select
. T his signal is used to interface the ADSP-2106x to synchronous
memory devices (including other ADSP-2106xs). T he ADSP-2106x asserts
SW
(low) to provide an
early indication of an impending write cycle, which can be aborted if
WR
is not later asserted (e.g., in a
conditional write instruction). In a multiprocessing system,
SW
is output by the bus master and is
input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write.
SW
is asserted at the same time as the address output. A host processor using synchronous writes must
assert this pin when writing to the ADSP-2106x(s).
Memory Acknowledge
. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off
completion of an external memory access. T he ADSP-2106x deasserts ACK as an output to add wait
states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-
2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its internal memory.
T he bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was
last driven.
TECHNICAL
devices or to the internal memory of other ADSP-2106xs. External devices must assert
WR
to write to
Pin
T ype
Function
ADDR
31-0
I/O/T
E xternal Bus Address
. T he ADSP-2106x outputs addresses for external memory and peripherals on
these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the internal
memory or IOP registers of other ADSP-2106xs. T he ADSP-2106x inputs addresses when a host
processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
E xternal Bus Data
. T he ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit
bus. 40-bit extended-precision floating-point data is transferred over bits 47–8 of the bus. 16-bit short
word data is transferred over bits 31–16 of the bus. In PROM boot mode, 8-bit data is transferred over
bits 23–16. Pull-up resistors on unused DAT A pins are not necessary.
Memory Select Lines
. T hese lines are asserted (low) as chip selects for the corresponding banks of
external memory. Memory bank size must be defined in the ADSP-2106x’s system control register
(SYSCON). T he
MS
3-0
lines are decoded memory address lines that change at the same time as the
other address lines. When no external memory access is occurring the
MS
3-0
lines are inactive; they are
active however when a conditional memory access instruction is executed, whether or not the condition
is true.
MS
0
can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a
multiprocessing system the
MS
3-0
lines are output by the bus master.
Memory Read Strobe
. T his pin is asserted (low) when the ADSP-2106x reads from external memory
devices or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-
2106xs) must assert
RD
to read from the ADSP-2106x’s internal memory. In a multiprocessing system
RD
is output by the bus master and is input by all other ADSP-2106xs.
Memory Write Strobe
. T his pin is asserted (low) when the ADSP-2106x writes to external memory
DAT A
47-0
I/O/T
MS
3-0
O/T
RD
I/O/T
WR
I/O/T
PAGE
O/T
ADRCLK
SW
O/T
I/O/T
ACK
I/O/S
PIN FUNCT ION DE SCRIPT IONS
ADSP-21060C pin definitions are listed below. All pins are
identical on the ADSP-21060C and ADSP-21060LC. Inputs
identified as synchronous (S) must meet timing requirements
with respect to CLK IN (or with respect to T CK for T MS,
T DI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLK IN (or to T CK for
TRST
).
Unused inputs should be tied or pulled to VDD or GND,
except for ADDR
31-0
, DAT A
47-0
, FLAG
3-0
,
SW
, and inputs that
have internal pull-up or pull-down resistors (
CPA
, ACK , DT x,
DRx, T CLK x, RCLK x, LxDAT 3-0, LxCLK , LxACK , T MS
and T DI)—these pins can be left floating. T hese pins have a
logic-level hold circuit that prevents the input from floating
internally.
A = Asynchronous
G = Ground
O = Output
P = Power Supply
(A/D) = Active Drive
(O/D) = Open Drain
T = T hree-State (when
SBTS
is asserted, or when the
ADSP-2106x is a bus slave)
I = Input
S = Synchronous
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