參數(shù)資料
型號(hào)： ADSP-21060LC
廠商： Analog Devices, Inc.
英文描述： DSP Microcomputer(DSP 微計(jì)算機(jī))
中文描述： 微機(jī)的DSP（數(shù)字信號(hào)處理器微計(jì)算機(jī)）
文件頁(yè)數(shù)： 11/48頁(yè)
文件大小： 515K
代理商： ADSP-21060LC
ADSP-21060C/ADSP-21060LC
–11–
REV. PrA
PRELIMINARY
DATA
TECHNICAL
T ARGE T BOARD CONNE CT OR FOR E Z-ICE
PROBE
T he ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JT AG test access port of the ADSP-2106x to monitor and control
the target board processor during emulation. T he EZ-ICE probe
requires the ADSP-2106x’s CLK IN, T MS, T CK ,
TRST
, T DI,
T DO,
EMU
, and GND signals be made accessible on the target
system via a 14-pin connector (a 2 row
×
7 pin strip header) such
as that shown in Figure 5. T he EZ-ICE
probe plugs directly onto
this connector for chip-on-board emulation. You must add this
connector to your target board design if you intend to use the
ADSP-2106x EZ-ICE. T he total trace length between the EZ-
ICE connector and the furthest device sharing the EZ-ICE
JT AG pins should be limited to 15 inches maximum for guaran-
teed operation. T his length restriction must include EZ-ICE
JT AG signals that are routed to one or more ADSP-2106x
devices, or a combination of ADSP-2106x devices and other
JT AG devices on the chain.
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
EMU
CLKIN (OPTIONAL)
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
Figure 5. Target Board Connector For ADSP-2106x EZ-ICE
Emulator (J umpers in Place)
E
T
T
E
T
ADSP-2106x
#1
JTAG
DEVICE
(OPTIONAL)
ADSP-2106x
n
TDI
EZ-ICE
JTAG
CONNECTOR
OTHER
JTAG
CONTROLLER
OPTIONAL
T
T
EMU
TRST
TMS
TCK
TDO
CLKIN
T
T
T
T
TDI
TDO
TDI
TDO
TDO
TDI
Figure 6. J TAG Scan Path Connections for Multiple ADSP-2106x Systems
T he 14-pin, 2-row pin strip header is keyed at the Pin 3 location —
Pin 3 must be removed from the header. T he pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1
×
0.1 inches. Pin strip headers are available from
vendors such as 3M, McK enzie and Samtec.
T he BT MS, BT CK ,
BTRST
and BT DI signals are provided so
the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If the test
access port will not be used for board testing, tie
BTRST
to GND
and tie or pull BT CK up to VDD. T he
TRST
pin must be
asserted after power-up (through
BTRST
on the connector) or
held low for proper operation of the ADSP-2106x. None of the
Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE
probe.
T he JT AG signals are terminated on the EZ-ICE probe as
follows:
Signal
T ermination
Driven through 22
Driven at 10 MHz through 22
Resistor (16 mA
Driver)
TRST
* Active Low Driven through 22
Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 k
Resistor)
T DI
Driven by 22
Resistor (16 mA Driver)
T DO
One T T L Load, Split T ermination (160/220)
CLK IN One T T L Load, Split T ermination (160/220)
EMU
Active Low 4.7 k
Pull-Up Resistor, One T T L Load
(Open-Drain Output from the DSP)
T MS
T CK
probe is turned on by the emulator at
TRST
is driven high.
Figure 6 shows JT AG scan path connections for systems that
contain multiple ADSP-2106x processors.
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