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參數資料
| 型號： | ADSP-21060LC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | DSP Microcomputer(DSP 微計算機) |
| 中文描述： | 微機的DSP（數字信號處理器微計算機） |
| 文件頁數： | 5/48頁 |
| 文件大?。?/td> | 515K |
| 代理商： | ADSP-21060LC |
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ADSP-21060C/ADSP-21060LC
–5–
REV. PrA
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.
DMA transfers can occur between the ADSP-2106x’s internal
memory and either external memory, external peripherals or a
host processor. DMA transfers can also occur between the
ADSP-2106x’s internal memory and its serial ports or link
ports. DMA transfers between external memory and external
peripheral devices are another option. External bus packing to
16-, 32-, or 48-bit words is performed during DMA transfers.
T en channels of DMA are available on the ADSP-2106x—two
via the link ports, four via the serial ports, and four via the
processor’s external port (for either host processor, other
ADSP-2106xs, memory or I/O transfers). Four additional link
port DMA channels are shared with serial port 1 and the exter-
nal port. Programs can be downloaded to the ADSP-2106x
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(
DMAR1-2
,
DMAG1-2
). Other DMA features include inter-
rupt generation upon completion of DMA transfers and DMA
chaining for automatic linked DMA transfers.
TECHNICAL
I/O is especially useful for point-to-point interprocessor commu-
nication in multiprocessing systems.
T he link ports can operate independently and simultaneously,
with a maximum data throughput of 240 Mbytes/s. Link port
data is packed into 32- or 48-bit words, and can be directly read
by the core processor or DMA-transferred to on-chip memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. T ransfers are programmable as either transmit or
receive.
Serial Ports
T he ADSP-2106x features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. T he serial ports can operate at
the full clock rate of the processor, providing each with a maxi-
mum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers T DM
multichannel mode.
T he serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. T hey offer selectable synchronization and transmit
modes as well as optional
μ
-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
Multiprocessing
T he ADSP-2106x offers powerful features tailored to multi-
Figure 4) allows direct interprocessor accesses of each ADSP-
2106x’s internal memory. Distributed bus arbitration logic is
included on-chip for simple, glueless connection of systems
containing up to six ADSP-2106xs and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus lock
allows indivisible
read-modify-write
sequences for semaphores. A
vector interrupt is provided for interprocessor commands. Maxi-
mum throughput for interprocessor data transfer is 240 Mbytes/s
over the link ports or external port.
Broadcast writes
allow simulta-
neous transmission of data to all ADSP-2106xs and can be used
to implement reflective semaphores.
Link Ports
T he ADSP-2106x features six 4-bit link ports that provide addi-
tional I/O capabilities. T he link ports can be clocked twice per
cycle, allowing each to transfer eight bits per cycle. Link port
Program Booting
T he internal memory of the ADSP-2106x can be booted at
system power-up from either an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the
BMS
(Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins.
32-bit and 16-bit host processors can be used for booting.
Off-Chip Memory and Peripherals Interface
T he ADSP-2106x’s external port provides the processor’s inter-
face to off-chip memory and peripherals. T he 4-gigaword off-
chip address space is included in the ADSP-2106x’s unified
address space. T he separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses, and I/O
data—are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. T he ADSP-2106x
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to DRAM
and peripherals with variable access, hold, and disable time
requirements.
Host Processor Interface
T he ADSP-2106x’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
T he host interface is accessed through the ADSP-2106x’s exter-
nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
T he host processor requests the ADSP-2106x’s external bus
with the host bus request (
HBR
), host bus grant (
HBG
), and
ready (REDY) signals. T he host can directly read and write the
internal memory of the ADSP-2106x, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
DMA Controller
T he ADSP-2106x’s on-chip DMA controller allows zero-
overhead data transfers without processor intervention. T he
DMA controller operates independently and invisibly to the
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| ADSP-21060LCB-133 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21060LCBZ-133 | 功能描述:IC DSP CONTROLLER 32BIT 225PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21060LCW-133 | 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 33MHz 33MIPS 240-Pin CQFP 制造商:Rochester Electronics LLC 功能描述:SHARC IND.,3V,33MHZ CQFP HEAT SLUG DOWN - Bulk |
| ADSP-21060LCW-160 | 功能描述:IC DSP CONTROLLER 32BIT 240CQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21060LCWZ-133 | 制造商:Analog Devices 功能描述:SHARC INDUSTRIAL 5V CQFP HEAT SLUG UP - Trays |
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