Table 12. MCS and fS Modes Master Clo" />
參數(shù)資料
型號(hào)： ADAU1966WBSTZRL
廠商： Analog Devices Inc
文件頁數(shù)： 9/52頁
文件大?。?/td> 0K
描述： IC DAC 24BIT DIFF 80LQFP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
數(shù)據(jù)接口： I²C，串行，SPI?
轉(zhuǎn)換器數(shù)目： 16
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 511mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 16 電壓，單極
采樣率（每秒）： *
Data Sheet
ADAU1966
Rev. D | Page 17 of 52
Table 12. MCS and fS Modes
Master Clock Select (MCS), PLL_CLK_CTRL0[2:1]
Sample Rate Select (FS)
Setting 0, b00
Setting 1, b01
Setting 2, b10
Setting 3, b11
DAC_CTRL0[2:1]
Ratio
MCLK (MHz)
Ratio
MCLK
Ratio
MCLK
Ratio
MCLK
32 kHz, b00
256 × fS
8.192
384 × fS
12.288
512 × fS
16.384
768 × fS
24.576
44.1 kHz, b00
256 × fS
11.2896
384 × fS
16.9344
512 × fS
22.5792
768 × fS
33.8688
48 kHz, b00
256 × fS
12.288
384 × fS
18.432
512 × fS
24.576
768 × fS
36.864
64 kHz, b01
128 × fS
8.192
192 × fS
12.288
256 × fS
16.384
384 × fS
24.576
88.2 kHz, b01
128 × fS
11.2896
192 × fS
16.9344
256 × fS
22.5792
384 × fS
33.8688
96 kHz, b01
128 × fS
12.288
192 × fS
18.432
256 × fS
24.576
384 × fS
36.864
128 kHz, b10 or b11
64 × fS
8.192
96 × fS
12.288
128 × fS
16.384
192 × fS
24.576
176.4 kHz, b10 or b11
64 × fS
11.2896
96 × fS
16.9344
128 × fS
22.5792
192 × fS
33.8688
192 kHz, b10 or b11
64 × fS
12.288
96 × fS
18.432
128 × fS
24.576
192 × fS
36.864
STANDALONE MODE
The ADAU1966 can operate without a typical I2C or SPI
connection to a microcontroller. This standalone mode is
made available by setting the SA_MODE (Pin 46) to high
(IOVDD). All registers are set to default except the options
Table 13. SA_MODE Settings
Pin No.
Setting
Function
42
0
Master mode serial audio interface (SAI)
1
Slave mode SAI
43
0
MCLK = 256 × fS, PLL on
1
MCLK = 384 × fS, PLL on
44
0
Must be set to 0
45
0
I2S SAI format
1
TDM modes, determined by Pin 31 and Pin 32
When both SA_MODE and Pin 45 are set high, TDM mode is
selected. Table 14 shows the available TDM modes; these modes
are set by connecting Pin 31 (DSDATA8) and Pin 32 (DSDATA7)
to GND or IOVDD.
Table 14. TDM Modes
Pin No.
Setting
Function
32:31
00
TDM4—DLRCLK pulse
01
TDM8—DLRCLK pulse
10
TDM16—DLRCLK pulse
11
TDM8—DLRCLK 50% duty cycle
When the ADAU1966 is powered up in SA_MODE and the
PU/RST pin is asserted high, the MCLKO pin provides a buff-
ered version of the MCLKI pin, whether the source is a crystal
or an active oscillator.
I2C CONTROL PORT
The ADAU1966 has an I2C-compatible control port that permits
programming and reading back of the internal control registers for
the DACs and clock system. The I2C interface of the ADAU1966 is
a 2-wire interface consisting of a clock line, SCL, and a data line,
SDA. SDA is bidirectional, and the ADAU1966 drives SDA
either to acknowledge the master (ACK) or to send data during
a read operation. The SDA pin for the I2C port is an open-drain
collector and requires a 2 kΩ pull-up resistor. A write or read
access occurs when the SDA line is pulled low while the SCL
line is high, indicated by a start in Figure 12 and Figure 13. SDA
is only allowed to change when SCL is low except when a start or
stop condition occurs, as shown in Figure 12 and Figure 13. The
first eight bits of the data-word consist of the device address and
the R/W bit. The device address consists of an internal built-in
address (0x04) and two address pins, ADDR1 and ADDR0. The
two address bits allow four ADAU1966 devices to be used in a
system. Initiating a write operation to the ADAU1966 involves
sending a start condition and then sending the device address
with the R/W bit set low. The ADAU1966 responds by issuing
an acknowledge to indicate that it has been addressed. The user
then sends a second frame telling the ADAU1966 which register
is required to be written. Another acknowledge is issued by the
ADAU1966. Finally, the user can send another frame with the
eight data bits required to be written to the register. A third
acknowledge is issued by the ADAU1966 after which the user
can send a stop condition to complete the data transfer.
A read operation requires that the user first write to the
ADAU1966 to point to the correct register and then read the
data. This is achieved by sending a start condition followed by
the device address frame, with the R/W bit low, and then the
register address frame. Following the acknowledge from the
ADAU1966, the user must issue a repeated start condition. The
next frame is the device address with the R/W bit set high. On
the next frame, the ADAU1966 outputs the register data on the
SDA line. A stop condition completes the read operation.
Table 15. I2C Addresses
ADDR1
ADDR0
Slave Address
0
0x04
0
1
0x24
1
0
0x44
1
0x64
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