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參數(shù)資料
| 型號： | ADAU1966WBSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 24BIT DIFF 80LQFP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 16 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 511mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 16 電壓，單極 |
| 采樣率（每秒）： | * |
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Data Sheet
ADAU1966
Rev. D | Page 11 of 52
Pin No.
Type1
Mnemonic
Description
20, 29, 41
PWR
DVDD
Digital Power, 2.5 V.
21, 26, 30, 40
GND
DGND
Digital Ground.
22, 39
PWR
IOVDD
Power for Digital Input and Output Pins, 3.3 V to 5 V.
23
I
VSENSE
2.5 V Output of Regulator, Collector of Pass Transistor. Bypass with 10 F in parallel
with 100 nF.
24
O
VDRIVE
Drive for Base of Pass Transistor.
25
I
VSUPPLY
5 V Input to Voltage Regulator, Emitter of Pass Transistor. Bypass with 10 F in parallel
with 100 nF.
27
I/O
DBCLK
Bit Clock for DACs.
28
I/O
DLRCLK
Frame Clock for DACs.
31
I
DSDATA8/SA
DAC15 and DAC 16 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 13, and Table 14).
32
I
DSDATA7/SA
DAC13 and DAC 14 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 13, and Table 14).
33
DSDATA6
DAC11 and DAC 12 Serial Data Input.
34
I
DSDATA5
DAC9 and DAC 10 Serial Data Input.
35
I
DSDATA4
DAC7 and DAC 8 Serial Data Input.
36
I
DSDATA3
DAC5 and DAC 6 Serial Data Input.
37
I
DSDATA2
DAC3 and DAC 4 Serial Data Input.
38
I
DSDATA1
DAC1 and DAC 2 Serial Data Input.
42
I
CDATA/ADDR1/SA
section and Table 13).
43
I/O
COUT/SDA/SA
Control Data Output (SPI)/Control Data Input (I2C)/SA_MODE State (see the
44
I
CCLK/SCL/SA
Mode section and Table 13).
45
I
CLATCH/ADDR0/SA
Control Chip Select (SPI) (Low Active)/Address 0 (I2C)/SA_MODE State (see the
46
I
SA_MODE
Standalone Mode. This pin allows mode control of ADAU1966 using Pin 42 to Pin 45,
Pin 31, and Pin 32 (high active, see Table 13 and Table 14).
47
I
PU/RST
Power-Up/Reset (Low Active).
48
GND
AGND1
Analog Ground.
49
PWR
AVDD1
Analog Power.
50
O
DAC1P
DAC1 Positive Output.
51
O
DAC1N
DAC1 Negative Output.
52
O
DAC2P
DAC2 Positive Output.
53
O
DAC2N
DAC2 Negative Output.
54
O
DAC3P
DAC3 Positive Output.
55
O
DAC3N
DAC3 Negative Output.
56
O
DAC4P
DAC4 Positive Output.
57
O
DAC4N
DAC4 Negative Output.
58
PWR
AVDD2
Analog Power.
59
I
DAC_BIAS1
DAC Bias 1. AC couple with 470 nF to AVDD2.
60
I
DAC_BIAS2
DAC Bias 2. AC couple with 470 nF to AGND2.
61
GND
AGND2
Analog Ground.
62
O
CM
Common-Mode Reference Filter Capacitor Connection. Bypass with 10 F in parallel
with 100 nF to AGND2. This reference can be shut off in the PLL_CLK_CTRL1 register
and the pin can be driven with an outside voltage source.
63
O
TS_REF
Voltage Reference Filter Capacitor Connection. Bypass with 10 F in parallel with
100 nF to AGND2.
64
O
DAC5P
DAC5 Positive Output.
65
O
DAC5N
DAC5 Negative Output.
66
O
DAC6P
DAC6 Positive Output.
67
O
DAC6N
DAC6 Negative Output.
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