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參數(shù)資料
| 型號： | ADAU1966WBSTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/52頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 24BIT DIFF 80LQFP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 16 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 511mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 16 電壓，單極 |
| 采樣率（每秒）： | * |
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ADAU1966
Data Sheet
Rev. D | Page 16 of 52
After the PU/RST pin has been asserted high, the PLL_CLK_
CTRLx registers (Register 0x00 and Register 0x01) can be
programmed. The on-chip phase-locked loop (PLL) can be
selected to use the clock appearing at the MCLKI/XTALI pin at
a frequency of 256, 384, 512, or 768 times the sample rate (fS),
referenced to the 48 kHz mode from the master clock select
(MCS) setting, as described in Table 12. In 96 kHz mode, the
master clock frequency stays at the same absolute frequency;
therefore, the actual multiplication rate is divided by 2. In
192 kHz mode, the actual multiplication rate is divided by 4.
the frequency of the master clock input is 256 × 48 kHz =
12.288 MHz. If the ADAU1966 is then switched to 96 kHz
operation (by writing to DAC_CTRL0 [2:1]), the frequency of
the master clock remains at 12.288 MHz, which is 128 × fS in this
example. In 192 kHz mode, MCS becomes 64 × fS.
The internal clock for the digital core varies by mode: 512 × fS
(48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz
mode). By default, the on-board PLL generates this internal
master clock from an external clock.
The PLL must be powered and stable before the ADAU1966 is
used as a source for quality audio. The PLL is enabled by reset
and does not require writing to the I2C or SPI port for normal
operation.
With the PLL enabled, the performance of the ADAU1966 is not
affected by jitter as high as a 300 ps rms time interval error
(TIE). If the internal PLL is not used, it is best to use an independ-
ent crystal oscillator to generate the master clock.
If the ADAU1966 is to be used in direct MCLK mode, the PLL can
be powered down in the PDN_THRMSENS_CTRL_1 register.
For direct MCLK mode, a 512 × fS (referenced to 48 kHz mode)
master clock must be used as MCLK, and the CLK_SEL bit in
the PLL_CLK_CTRL1 register must be set to b1.
The ADAU1966 PLL can also be programmed to run from an
external LRCLK. When the PLLIN bits in the PLL_CLK_CTRL0
register are set to 01 and the appropriate loop filter is connected
to the LF pin (see Figure 8), the ADAU1966 PLL generates all
of the necessary internal clocks for operation with no external
MCLK. This mode reduces the number of high frequency
signals in the design, reducing EMI emissions.
It is possible to further reduce EMI emissions of the circuit by
using the internal DBCLK generation setting of the BCLK_GEN
bit in the DAC_CTRL1 register. With the BCLK_GEN bit set to
b1 (internal) and the SAI_MS bit set to b0 (slave), the ADAU1966
generate its own DBCLK; this works with the PLL input set to
either MCLKI/XTALI or DLRCLK. DLRCLK is the only required
clock in DLRCLK PLL mode.
POWER-UP AND RST
Power sequencing for the ADAU1966 starts with AVDD and
IOVDD, followed by DVDD. It is very important that AVDD be
settled at a regulated voltage and that IOVDD be within 10% of
regulated voltage before applying DVDD. When using the
ADAU1966 internal regulator, this timing occurs by default.
To guarantee proper startup, the PU/RST pin must be pulled
low by an external resistor and then driven high after the power
supplies stabilize. The PU/RST can also be pulled high using a
simple RC network.
Driving the PU/RST pin low puts the part into a very low power
state (<3 A). All functionality of the ADAU1966 is disabled
until the PU/RST pin is asserted high. Once this pin is asserted
high, the ADAU1966 requires 300 ms to stabilize. The MMUTE
bit in the DAC_CTRL0 register must be toggled for operation.
The PUP bit in the PLL_CLK_CTRL0 register can be used to
power down the ADAU1966. Engaging the master power-down
puts the ADAU1966 in an idle state while maintaining the set-
tings of all registers. Additionally, the power-down bits in the
PDN_THRMSENS_CTRL1 register (TS_PDN, PLL_PDN, and
VREG_PDN) can be used to power down individual sections of
The SOFT_RST bit in the PLL_CLK_CTRL0 register sets all of
the control registers to their default settings while maintaining
the internal clocks in default mode. The SOFT_RST bit does
not power down the analog outputs; toggling this bit does not
cause audible popping sounds at the differential analog outputs.
Proper startup of the ADAU1966 proceeds as follows:
1. Apply power to the ADAU1966 as described previously.
2. Assert the PU/RST pin high after power supplies have
stabilized.
3. Set the PUP bit to b1.
4. Program all necessary registers for the desired settings.
5. Set the MMUTE bit to b0 to unmute all channels.
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