參數(shù)資料
型號(hào): ADAU1966WBSTZRL
廠商: Analog Devices Inc
文件頁數(shù): 26/52頁
文件大?。?/td> 0K
描述: IC DAC 24BIT DIFF 80LQFP
標(biāo)準(zhǔn)包裝: 1,000
位數(shù): 24
數(shù)據(jù)接口: I²C,串行,SPI?
轉(zhuǎn)換器數(shù)目: 16
電壓電源: 模擬和數(shù)字
功率耗散(最大): 511mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 16 電壓,單極
采樣率(每秒): *
ADAU1966
Data Sheet
Rev. D | Page 32 of 52
DAC CONTROL 1 REGISTER
Address: 0x07, Reset: 0x00, Name: DAC_CTRL1
Table 31. Bit Descriptions for DAC_CTRL1
Bits
Bit Name
Settings
Description
Reset
Access
7
BCLK_GEN
DBCLK Generation. When the PLL is locked to DLRCLK, it is possible to run
the ADAU1966 without an external DBCLK.
0x0
RW
0
Normal Operation—DBCLK
1
Internal DBCLK Generation
6
LRCLK_MODE
DLRCLK Mode Select. Only Valid for TDM modes.
0x0
RW
0
50% Duty Cycle DLRCLK
1
Pulse Mode
5
LRCLK_POL
DLRCLK Polarity. Allows the swapping of data between channels.
0x0
RW
0
Left/Odd channels are DLRCLK Low (Normal)
1
Left/Odd channels are DLRCLK High (Inverted)
4
SAI_MSB
MSB Position.
0x0
RW
0
MSB First DSDATA
1
LSB First DSDATA
2
BCLK_RATE
DBCLK Rate. Number of DBCLK cycles per DLRCLK Frame. Used only for
generating DBCLK in Master Mode operation (SAI_MS = 1).
0x0
RW
0
32 Cycles per Frame
1
16 Cycles per Frame
1
BCLK_EDGE
DBCLK Active Edge. Adjust the polarity of the DBCLK leading edge.
0x0
RW
0
Latch in Rising Edge
1
Latch in Falling Edge
0
SAI_MS
Serial Interface Master. Both DLRCLK and DBCLK become master when
enabled.
0x0
RW
0
DLRCLK/DBCLK Slave
1
DLRCLK/DBCLK Master
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