參數(shù)資料
型號(hào)： ADAU1966WBSTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/52頁(yè)
文件大?。?/td> 0K
描述： IC DAC 24BIT DIFF 80LQFP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 24
數(shù)據(jù)接口： I²C，串行，SPI?
轉(zhuǎn)換器數(shù)目： 16
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 511mW
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類(lèi)型： 16 電壓，單極
采樣率（每秒）： *
Data Sheet
ADAU1966
Rev. D | Page 19 of 52
SERIAL CONTROL PORT: SPI CONTROL MODE
The ADAU1966 has an SPI control port that permits program-
ming and readback of the internal control registers for the
DACs and clock system. A standalone mode is also available for
operation without serial control; it is configured at reset using the
SA_MODE pin. See the Standalone Mode section for details
about SA_MODE.
By default, the ADAU1966 is in I2C mode; however, SPI control
mode can be entered by pulling CLATCH low three times. To
enter SPI control mode, perform three dummy writes to the SPI
port (the ADAU1966 does not acknowledge these three writes).
Beginning with the fourth SPI write, data can be written to or
read from the IC. The ADAU1966 can exit SPI control mode
only by a full reset initiated by power cycling the device.
The SPI control port of the ADAU1966 is a 4-wire serial control
port. The format is a 24-bit wide data-word. The serial bit clock
and latch can be completely asynchronous to the sample rate of
the DACs. Table 21 shows the format of the SPI address byte.
The first byte is the global address with a read/write bit. For the
ADAU1966, the address is Address 0x06, shifted left one bit due
to the R/W bit. The second byte is the ADAU1966 register
address, and the third byte is the data, as shown in Figure 15
Table 21. SPI Address and R/W Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
1
0
R/W
When reading data from the ADAU1966, the COUT pin is
tristated until the third byte, at which point it drives the data
out (see Figure 16). The COUT pin is tristated at all other times,
allowing the pin to be bussed with other devices, see Figure 17
for the timing requirements.
Chip Address R/W
The LSB of the first byte of a SPI transaction is an R/W bit. This
bit determines whether the communication is a read (Logic
Level 1) or a write (Logic Level 0); see Table 21 for this format.
SPI Burst Read/Write
The SPI port is capable of performing burst reads or writes.
This is accomplished by sending the chip address byte with the
R/W bit, followed by the first register address that needs to be
read or written to. Then, as long as the CLATCH pin is held
low, registers can be sequentially read or written by continuing
to send out clock pulses into the CCLK pin. A very efficient
procedure to initialize the ADAU1966 is accomplished by
1. Sending out the address byte with the R/W bit low (write).
2. Sending out the address of the first register.
3. Sending out all the register byte values.
4. Toggling the CLATCH pin.
5. Performing a burst read to verify the register writes.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CLATCH
CCLK
CDATA
09434-
1
14
Figure 14. SPI Mode Initial Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CLATCH
CCLK
CDATA
REGISTER ADDRESS BYTE
DEVICE ADDRESS (7 BITS)
R/W
DATA BYTE
09434-
1
15
Figure 15. SPI Write to ADAU1966 Clocking
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CLATCH
CCLK
CDATA
COUT
REGISTER ADDRESS BYTE
DEVICE ADDRESS (7 BITS)
R/W
DATA BYTE
DATA BYTE FROM ADAU1966
09434-
1
16
Figure 16. SPI Read from the ADAU1966 Clocking
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