參數(shù)資料
型號： AD9518-0A/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 57/64頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9518-0A
設(shè)計資源： AD9518 Eval Brd Schematics
AD9518 Gerber Files
AD9518-0 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計時，時鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9518-0A
主要屬性： 2 輸入，6 輸出，2.8GHz VCO
次要屬性： LVPECL 輸出邏輯
已供物品： 板
AD9518-0
Data Sheet
Rev. C | Page 60 of 64
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs (because they are open emitter) require
a dc termination to bias the output transistors. The simplified
equivalent circuit in Figure 43 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 53) or Y-termination (see Figure 54) is recommended.
In each case, the VS of the receiving buffer should match the
VS_LVPECL voltage. If it does not, ac coupling is recommended (see
Figure 55). In the case of Figure 55, pull-down resistors of <150
are not recommended when VS_LVPECL = 3.3 V; if used, damage to
the LVPECL drivers may result. The minimum recommended
pull-down resistor size for VS_LVPECL = 2.5 V is 100 .
The resistor network is designed to match the transmission line
impedance (50 ) and the switching threshold (VS 1.3 V).
VS_LVPECL
LVPECL
50
SINGLE-ENDED
(NOT COUPLED)
VS
VS_DRV
LVPECL
127
83
06429-
145
Figure 53. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
VS_LVPECL
LVPECL
Z0 = 50
VS = 3.3V
LVPECL
50
Z0 = 50
06429-
147
Figure 54. DC-Coupled 3.3 V LVPECL Y-Termination
VS_LVPECL
LVPECL
100 DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
VS
LVPECL
100
0.1nF
200
06429-
146
Figure 55. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 54, where VS_LVPECL = 2.5 V, the 50 termination
resistor that is connected to ground should be changed to 19 .
Thevenin-equivalent termination uses a resistor network to provide
50 termination to a dc voltage that is below VOL of the LVPECL
driver. In this case, VS_LVPECL on the AD9518 should equal VS of
the receiving buffer. Although the resistor combination shown
in Figure 54 results in a dc bias point of VS_LVPECL 2 V, the actual
common-mode voltage is VS_LVPECL 1.3 V because there is
additional current flowing from the AD9518 LVPECL driver
through the pull-down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that the pull-
down resistor is 62.5 and the pull-up resistor is 250 .
相關(guān)PDF資料
PDF描述
FCBP110LD1L10S KIT 10M LASERWIRE SFP+
VE-JTX-EZ-S CONVERTER MOD DC/DC 5.2V 25W
H3CWH-2036M IDC CABLE - HKC20H/AE20M/HPL20H
AD9518-3A/PCBZ BOARD EVALUATION FOR AD9518-3A
AD9518-4A/PCBZ BOARD EVALUATION FOR AD9518-4A
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9518-0BCPZ 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP Tray
AD9518-0BCPZ-REEL7 制造商:Analog Devices 功能描述:
AD9518-1 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 2.5 GHz VCO
AD9518-1/PCBZ 制造商:Analog Devices 功能描述:6-Output Clock Generator with 2.8GHz
AD9518-1A/PCBZ 功能描述:BOARD EVALUATION FOR AD9518-1A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*