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| 型號： | AD9518-0A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9518-0A |
| 設計資源： | AD9518 Eval Brd Schematics AD9518 Gerber Files AD9518-0 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9518-0A |
| 主要屬性： | 2 輸入，6 輸出，2.8GHz VCO |
| 次要屬性： | LVPECL 輸出邏輯 |
| 已供物品： | 板 |
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AD9518-0
Data Sheet
Rev. C | Page 38 of 64
A sync operation brings all outputs that have not been excluded
(by the nosync bit) to a preset condition before allowing the outputs
to begin clocking in synchronicity. The preset condition takes
into account the settings in each of the channel’s start high bit
and its phase offset. These settings govern both the static state
of each output when the sync operation is happening and the
state and relative phase of the outputs when they begin clocking
again upon completion of the sync operation. Between outputs
and after synchronization, this allows for the setting of phase
offsets.
The AD9518 outputs are in pairs, sharing a channel divider
per pair. The synchronization conditions apply to both outputs
of a pair.
Each channel (a divider and its outputs) can be excluded from
any sync operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do not
set their outputs static during a sync operation, and their outputs
are not synchronized with those of the nonexcluded channels.
LVPECL Outputs—OUT0 to OUT3
The LVPECL differential voltage (VOD) is selectable from ~400 mV
to ~960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]).
The LVPECL outputs have dedicated pins for power supply
(VS_LVPECL), allowing a separate power supply to be used.
VS_LVPECL can be from 2.5 V to 3.3 V.
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring
a board layout change. Each LVPECL output can be powered
down or powered up, as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have several power-down
modes. This includes a safe power-down mode that continues
to protect the output devices while powered down, although it
consumes somewhat more power than a total power-down. If
the LVPECL output pins are terminated, it is best to select the
safe power-down mode. If the pins are left floating (that is, not
connected), total power-down mode is fine.
GND
3.3V
OUT
06429-
033
Figure 43. LVPECL Output Simplified Equivalent Circuit
RESET MODES
The AD9518 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Power-On Reset—Start-Up Conditions When VS Is Applied
A power-on reset (POR) is issued when the VS power supply is
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the Default Value (Hex) column of Table 42. At
power-on, the AD9518 also executes a sync operation, which
brings the outputs into phase alignment according to the default
settings.
Asynchronous Reset via the RESET Pin
An asynchronous hard reset is executed by momentarily pulling
RESET low. A reset restores the chip registers to the default settings.
Soft Reset via Register 0x000[2]
A soft reset is executed by writing Register 0x000[2] and
Register 0x000[5] = 1b. This bit is not self-clearing; it must be
cleared by writing Register 0x000[2] and Register 0x000[5] = 0b to
reset it and complete the soft reset operation. A soft reset restores
the default values to the internal registers. The soft reset bit does
not require an update registers command (Register 0x232) to be
issued.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9518 can be put into a power-down condition by
pulling the PD pin low. Power-down turns off most of the
functions and currents inside the AD9518. The chip remains in
this power-down state until PD is brought back to logic high.
When the AD9518 wakes up, it returns to the settings programmed
into its registers prior to the power-down, unless the registers
are changed by new programming while the PD pin is held low.
The PD power-down shuts down the currents on the chip,
except the bias current that is necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tristated.
Because this is not a complete power-down, it can be called
sleep mode.
When the AD9518 is in a PD power-down, the chip is in the
following state:
The PLL is off (asynchronous power-down).
The VCO is off.
The CLK input buffer is off.
All dividers are off.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
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