參數(shù)資料
型號: AD9518-0A/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 11/64頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9518-0A
設(shè)計資源: AD9518 Eval Brd Schematics
AD9518 Gerber Files
AD9518-0 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9518-0A
主要屬性: 2 輸入,6 輸出,2.8GHz VCO
次要屬性: LVPECL 輸出邏輯
已供物品:
Data Sheet
AD9518-0
Rev. C | Page 19 of 64
–120
–160
–150
–140
–130
1k
100M
10M
1M
100k
10k
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
06429-
141
Figure 23. Phase Noise (Absolute) Clock Generation; Internal VCO at 2.7 GHz;
PFD = 15.36 MHz; LBW = 110 kHz; LVPECL Output = 122.88 MHz
–90
–100
–110
–120
–130
–140
–150
–160
1k
100M
10M
1M
100k
10k
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
06429-
139
Figure 24. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 2.8 GHz;
PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
–120
–160
–150
–140
–130
1k
100M
10M
1M
100k
10k
PH
A
SE
N
O
ISE
(d
B
c
/H
z)
FREQUENCY (Hz)
06429-
140
Figure 25. Phase Noise (Absolute); External VCXO (Toyocom TCO-2112) at
245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
1000
100
10
1
0.1
0.01
0.1
1
10
100
1000
IN
P
U
T
J
ITTE
R
A
M
P
LITU
D
E
(
U
Ip-
p)
JITTER FREQUENCY (kHz)
06429-
148
OC-48 OBJECTIVE MASK
AD9518
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
fOBJ
Figure 26. GR-253 Jitter Tolerance Plot
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