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參數(shù)資料
型號(hào): AD9518-0A/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 38/64頁
文件大小: 0K
描述: BOARD EVALUATION FOR AD9518-0A
設(shè)計(jì)資源: AD9518 Eval Brd Schematics
AD9518 Gerber Files
AD9518-0 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9518-0A
主要屬性: 2 輸入,6 輸出,2.8GHz VCO
次要屬性: LVPECL 輸出邏輯
已供物品:
Data Sheet
AD9518-0
Rev. C | Page 43 of 64
CS
SCLK
SDIO
tHIGH
tLOW
tCLK
tS
tDS
tDH
tC
BIT N
BIT N + 1
06429-
043
Figure 51. Serial Control Port Timing Diagram—Write
Table 40. Serial Control Port Timing
Parameter
Description
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tCLK
Period of the clock
tS
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
tC
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
tHIGH
Minimum period that SCLK should be in a logic high state
tLOW
Minimum period that SCLK should be in a logic low state
tDV
SCLK to valid SDIO and SDO (see Figure 49)
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