參數(shù)資料
型號(hào)： AD9518-0A/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/64頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR AD9518-0A
設(shè)計(jì)資源： AD9518 Eval Brd Schematics
AD9518 Gerber Files
AD9518-0 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9518-0A
主要屬性： 2 輸入，6 輸出，2.8GHz VCO
次要屬性： LVPECL 輸出邏輯
已供物品： 板
Data Sheet
AD9518-0
Rev. C | Page 3 of 64
REVISION HISTORY
1/12—Rev. B to Rev. C
Change to 0x232 Description, Table 49........................................58
9/11—Rev. A to Rev. B
Changes to Applications and General Description Sections.......1
Change to CPRSET Pin Resistor Parameter, Table 1....................4
Changes to Table 2 ............................................................................4
Change to Test Conditions/Comments Column of Output
Differential Voltage (VOD) Parameter, Table 4...............................5
Change to Logic 1 Current and Logic 0 Current Parameters,
Table 14.............................................................................................10
Change to Test Conditions/Comments Column of LVPECL
Channel (Divider Plus Output Driver) Parameter, Table 16.....11
Changes to Table 19 ........................................................................14
Changes to Captions, Figure 11 and Figure 16............................17
Added Figure 26, Renumbered Sequentially...............................19
Change to PLL External Loop Filter Section...............................27
Changes to Reference Switchover and Prescaler Sections .........28
Changes to Comments/Conditions Column, Table 27 ..............29
Changes to Automatic/Internal Holdover Mode and
Frequency Status Monitors Sections.............................................32
Changes to VCO Calibration Section...........................................33
Changes to Clock Distribution Section........................................34
Change to Write Section.................................................................40
Change to Figure 47 ........................................................................42
Changes to Table 41 ........................................................................44
Changes to Register Address 0x01C, Table 42 ............................45
Changes to Register Address 0x017, Bits[1:0] and
Register Address 0x018, Bits[2:0], Table 44.................................50
Changes to Register Address 0x01C, Bits[5:1], Table 44............53
Change to Bit 5, Register Address 0x191, Register
Address 0x194, and Register Address 0x197, Table 46...............56
Changes to LVPECL Clock Distribution Section .......................60
Updated Outline Dimensions and Changes to
Ordering Guide ...............................................................................61
1/10—Rev. 0 to Rev. A
Added 48-Lead LFCSP Package (CP-48-8) ....................Universal
Changes to Features, Applications, and General Description.....1
Change to CPRSET Pin Resistor Parameter..................................4
Changes to VCP Supply Parameter.................................................11
Changes to Table 18 ........................................................................13
Added Exposed Paddle Notation to Figure 4;
Changes to Table 19 ........................................................................14
Change to High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz Section; Change to Table 21..........22
Changes to Table 23 ........................................................................24
Change to Configuration and Register Settings Section ...........25
Change to Phase Frequency Detector (PFD) Section ................26
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections .........27
Change to Figure 31; Added Figure 32.........................................27
Changes to Reference Switchover and Prescaler Sections.........28
Changes to A and B Counters Section and Table 27..................29
Change to Holdover Section..........................................................31
Changes to VCO Calibration Section...........................................33
Changes to Clock Distribution Section........................................34
Change to Table 32; Change to Channel Frequency
Division (0, 1, and 2) Section ........................................................35
Change to Write Section ................................................................40
Change to Figure 46........................................................................42
Added Thermal Performance Section; Added Table 41 ............44
Changes to 0x003 Register Address..............................................45
Changes to Table 43 ........................................................................47
Changes to Table 44 ........................................................................48
Changes to Table 45 ........................................................................55
Changes to Table 46 ........................................................................57
Changes to Table 47 ........................................................................58
Changes to Table 48 ........................................................................59
Added Frequency Planning Using the AD9518 Section............60
Changes to LVDS Clock Distribution Section ............................61
Changes to Figure 52 and Figure 54; Added Figure 53..............61
Added Exposed Paddle Notation to Outline Dimensions;
Changes to Ordering Guide...........................................................62
8/07—Revision 0: Initial Version
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