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參數(shù)資料
型號(hào)： AD5590BBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 44/44頁(yè)
文件大小： 0K
描述： IC ADC I/O PORT-16 AMP 80-CSPBGA
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 12.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 80-CSP-BGA（10x10）
包裝： 托盤
輸入數(shù)目和類型： 16 個(gè)單端，單極
產(chǎn)品目錄頁(yè)面： 777 (CN2011-ZH PDF)
AD5590
Rev. A | Page 9 of 44
TIMING SPECIFICATIONS
ADC Timing Characteristics
ADCVDD = 2.7 V to 5.25 V, VDRIVE ≤ ADCVDD, VREFA = 2.5 V; All specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter1
Limit at TMIN, TMAX; ADCVDD = 5 V
Unit
Conditions/Comments
fSCLK2
10
kHz min
20
MHz min
tCONVERT
16 × tASCLK
MHz max
tQUIET
50
ns min
t2
10
ns min
ASYNC to ASCLK setup time
14
ns max
Delay from ASYNC until ADOUT three-state disabled
t3b4
20
ns min
Data hold time
40
ns max
Data access time after ASCLK falling edge
t5
0.4 × tASCLK
ns min
ASCLK low pulse width
t6
0.4 × tASCLK
ns min
ASCLK high pulse width
t7
15
ns min
ASCLK to ADOUT valid hold time
15/50
ns min/max
ASCLK falling edge to ADOUT high impedance
t9
20
ns min
ADIN setup time prior to ASCLK falling edge
t10
5
ns min
ADIN Hold time prior to ASCLK falling edge
t11
20
ns min
16th ASCLK falling edge to ASYNC high
t12
1
s max
Power-up time from full power-down/autoshutdown/
autostandby modes
1
Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of ADCVDD) and timed from a voltage
level of 1.6 V.
2
Maximum ASCLK frequency is 50 MHz at ADCVDD = 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
3
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 × VDRIVE.
4
t3b represents a worst-case figure for having ADD3 available on the ADOUT line, that is, if the ADC goes back into three-state at the end of a conversion and some
other device takes control of the bus between conversions, the user needs to wait a maximum time of t3b before having ADD3 valid on the ADOUT line. If the ADOUT
line is weakly driven to ADD3 between conversions, then the user typically needs to wait 17 ns at 3 V and 12 ns at 5 V after the ASYNC falling edge before seeing ADD3
valid on ADOUT.
5
t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of bus loading.
ASCLK
ADOUT
ADIN
ASYNC
WRITE
SEQ
ADD3
ADD2
ADD1
ADD0
DONTC
ADD2
ADD1
ADD0
DB11
DB10
DB2
DB1
DB0
B
t2
t3b
t3
1
2
3
4
5
6
13
14
15
16
t9
t10
t8
t4
t7
t6
t5
t11
tQUIET
tCONVERT
THREE-
STATE
THREE-
STATE ADD3
FOUR IDENTIFICATION BITS
07691-
002
Figure 2. ADC Timing Characteristics
200A
IOL
200A
IOH
1.6V
TO OUTPUT
PIN
CL
25pF
07691-
003
Figure 3. Load Circuit for ADC Digital Output Timing Specifications
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