參數(shù)資料
型號: AD5590BBCZ
廠商: Analog Devices Inc
文件頁數(shù): 1/44頁
文件大小: 0K
描述: IC ADC I/O PORT-16 AMP 80-CSPBGA
標(biāo)準(zhǔn)包裝: 1
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 12.5mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 80-CSP-BGA(10x10)
包裝: 托盤
輸入數(shù)目和類型: 16 個單端,單極
產(chǎn)品目錄頁面: 777 (CN2011-ZH PDF)
16 Input, 16 Output Analog I/O Port
with Integrated Amplifiers
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2008–2011 Analog Devices, Inc. All rights reserved.
FEATURES
Input channels
12-bit successive approximation ADC
16 inputs with sequencer
Fast throughput rate: 1 MSPS
Wide input bandwidth: 70 dB SNR at fIN = 50 kHz
Output channels
16 outputs with 12-bit DACs
On-chip 2.5 V reference
Hardware LDAC and LDAC override function
CLR function to programmable code
Rail-to-rail operation
Operational amplifiers
Offset voltage: 2.2 mV maximum
Low input bias current: 1 pA maximum
Single supply operation
Low noise: 22 nV/√Hz
Unity gain stable
Flexible serial interface
SPI-/QSPI-/MICROWIRE-/DSP-compatible
40°C to +85°C operation
Available in 80-ball CSP_BGA package
APPLICATIONS
Optical line cards
Base stations
General-purpose analog I/O
Monitoring and control
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER
DDIN
LDAC
VOUT7
ADCVDD
LDAC
VREFIN1/VREFOUT1
DSYNC1
DSCLK
AD5590
CLR
2.5V REF
VOUT0
DAC
REGISTER
STRING
DAC 0
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 7
BUFFER
POWER-DOWN
LOGIC
POWER-ON
RESET
DAC
INTERFACE
LOGIC
IN0(–) IN0(+)
OUT0
IN7(–) IN7(+)
OUT7
VIN0
VIN15
INPUT
MUX
T/H
ASCLK
ASYNC
SEQUENCER
VREFA
VDRIVE
DACGND (×2)
DSYNC2
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
INTERFACE
LOGIC
ADIN
ADOUT
INPUT
REGISTER
VOUT15
VOUT8
DAC
REGISTER
STRING
DAC 8
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 15
BUFFER
VREFIN2/VREFOUT2
POWER-DOWN
LOGIC
2.5V REF
DACVDD (×2)
ADCGND
V1+ V2+ V1– V2–
07691-
001
Figure 1.
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