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參數(shù)資料
| 型號： | AD5590BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC I/O PORT-16 AMP 80-CSPBGA |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 12.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LFBGA，CSPBGA |
| 供應商設(shè)備封裝： | 80-CSP-BGA（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 16 個單端，單極 |
| 產(chǎn)品目錄頁面： | 777 (CN2011-ZH PDF) |
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AD5590
Rev. A | Page 3 of 44
GENERAL DESCRIPTION
The AD5590 is a 16-channel input and 16-channel output
analog I/O port with eight uncommitted amplifiers, operating
from a single 4.5 V to 5.25 V supply. The AD5590 comprises
16 input channels multiplexed into a 1 MSPS, 12-bit successive
approximation ADC with a sequencer to allow a preprogrammed
selection of channels to be converted sequentially. The ADC
contains a low noise, wide bandwidth track-and-hold amplifier
that can handle input frequencies in excess of 1 MHz.
The conversion process and data acquisition are controlled using
ASYNC and the serial clock signal, allowing the device to easily
interface with microprocessors or DSPs. The input signal is
sampled on the falling edge of ASYNC and conversion is also
initiated at this point. There are no pipeline delays associated
with the ADC. By setting the relevant bits in the control register,
the analog input range for the ADC can be selected to be a 0 V
to VREFA input or a 0 V to 2 × VREFA with either straight binary
or twos complement output coding. The conversion time is
determined by the ASCLK frequency because it is also used
as the master clock to control the conversion.
The DAC section of the AD5590 comprises sixteen 12-bit DACs
divided into two groups of eight. Each group has an on-chip
reference. The on-board references are off at power-up, allowing
the use of external references. The internal references are enabled
via a software write.
The AD5590 incorporates a power-on reset circuit that ensures
that the DAC outputs power up to 0 V and remain powered up
at this level until a valid write takes place. The DAC contains a
power-down feature that reduces the current consumption of
the device and provides software-selectable output loads while
in power-down mode for any or all DAC channels. The outputs
of all DACs can be updated simultaneously using the LDAC
function, with the added functionality of user-selectable DAC
channels to simultaneously update. There is also an asynchronous
CLR that updates all DACs to a user-programmable code: zero
scale, midscale, or full scale.
The AD5590 contains eight low noise, single-supply amplifiers.
These amplifiers can be used for signal conditioning for the
ADCs, DACs, or other independent circuitry, if required.
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