參數(shù)資料
型號(hào)： AD5590BBCZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/44頁(yè)
文件大小： 0K
描述： IC ADC I/O PORT-16 AMP 80-CSPBGA
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 12.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 80-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 80-CSP-BGA（10x10）
包裝： 托盤
輸入數(shù)目和類型： 16 個(gè)單端，單極
產(chǎn)品目錄頁(yè)面： 777 (CN2011-ZH PDF)
AD5590
Rev. A | Page 36 of 44
Powering Up the ADC
When supplies are first applied to the ADC, the ADC can
power up in any of the operating modes of the ADC. To ensure
that the ADC is placed into the required operating mode, the
user should perform a dummy cycle operation, as outlined in
The three dummy conversion operations outlined in Figure 68
must be performed to place the ADC into either of the
automatic modes. The first two conversions of this dummy
cycle operation are performed with the ADIN line tied high,
and for the third conversion of the dummy cycle operation, the
user writes the desired control register configuration to the
ADC to place the ADC into the required automode. On the
third ASYNC rising edge after the supplies are applied, the
control register contains the correct information and valid data
results from the next conversion.
Therefore, to ensure the ADC is placed into the correct
operating mode when supplies are first applied to the ADC,
the user must first issue two serial write operations with the
ADIN line tied high. On the third conversion cycle, the user
can then write to the ADC control register to place the ADC
into any of the operating modes. To guarantee that the ADC
control register contains the correct data, do not write to the
shadow register until the fourth conversion cycle after the
supplies are applied to the ADC.
If the user wants to place the ADC into either normal mode or
full shutdown mode, the second dummy cycle with ADIN tied
high can be omitted from the three dummy conversion opera-
tion outlined in Figure 68.
Interfacing to the ADC
Figure 2 shows the detailed timing diagram for serial inter-
facing to the ADC. The serial clock provides the conversion
clock and also controls the transfer of information to and from
the ADC during each conversion.
The ASYNC signal initiates the data transfer and conversion
process. The falling edge of ASYNC puts the track and hold
into hold mode, takes the bus out of three-state, and the analog
input is sampled at this point. The conversion is also initiated
at this point and requires 16 ASCLK cycles to complete. The
track and hold returns to track on the 14th ASCLK falling edge
as shown in Figure 2 at Point B, except when the write is to the
shadow register, in which case the track and hold does not
return to track until the rising edge of ASYNC, that is, Point C
in Figure 72. On the 16th ASCLK falling edge, the ADOUT line
goes back into three-state (assuming the weak/TRI bit is set
to 0). Sixteen serial clock cycles are required to perform the
conversion process and to access data from the ADC. The
12 bits of data are preceded by the four channel address bits
(ADD3 to ADD0), identifying which channel the conversion
result corresponds to. ASYNC going low provides Address
Bit ADD3 to be read in by the microprocessor or DSP. The
remaining address bits and data bits are then clocked out by
subsequent ASCLK falling edges beginning with the second
Address Bit ADD2; thus, the first ASCLK falling edge on the
serial clock has Address Bit ADD3 provided and also clocks out
Address Bit ADD2. The final bit in the data transfer is valid on
the 16th falling edge, having being clocked out on the previous
(15th) falling edge.
ASCLK
1
12
16
1
12
16
1
12
16
ADOUT
ADIN
ASYNC
DUMMY CONVERSION
CORRECT VALUE IN CONTROL
REGISTER VALID DATA FROM
NEXT CONVERSION USER CAN
WRITE TO SHADOW REGISTER
IN NEXT CONVERSION
INVALID DATA
DATA IN TO CONTROL
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCK EDGES
KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS
07691-
068
Figure 68. Placing the ADC into the Required Operating Mode after Supplies are Applied
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