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參數資料
| 型號： | AD14160LKB-4 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, CBGA452 |
| 封裝： | CERAMIC, BGA-452 |
| 文件頁數： | 9/52頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | AD14160LKB-4 |
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AD14160/AD14160L
–9–
REV. A
Pin
Type
Function
SBTS
I/S
Suspend Bus Three-State.
(Common to all SHARCs) External devices can assert
SBTS
(low) to
place the external bus address, data, selects, and strobes in a high impedance state for the following cycle.
If the AD14160/AD14160L attempts to access external memory while
SBTS
is asserted, the processor
will halt and the memory access will not be completed until
SBTS
is deasserted.
SBTS
should only be
used to recover from host processor/AD14160/AD14160L deadlock, or used with a DRAM controller.
Host Bus Request.
(Common to all SHARCs) Must be asserted by a host processor to request control
of the AD14160/AD14160L’s external bus. When
HBR
is asserted in a multiprocessing system, the
ADSP-2106x that is bus master will relinquish the bus and assert
HBG
. To relinquish the bus, the
ADSP-2106x places the address, data, select, and strobe lines in a high impedance state.
HBR
has priority
over all ADSP-2106x bus requests (
BR
6-1
) in a multiprocessing system.
Host Bus Grant.
(Common to all SHARCs)
Acknowledges an
HBR
bus request, indicating that the
host processor may take control of the external bus.
HBG
is asserted (held low) by the AD14160/
AD14160L until
HBR
is released. In a multiprocessing system,
HBG
is output by the ADSP-2106x bus
master and is monitored by all others.
Chip Select.
Asserted by host processor to select SHARC_A.
Chip Select.
Asserted by host processor to select SHARC_B.
Chip Select.
Asserted by host processor to select SHARC_C.
Chip Select.
Asserted by host processor to select SHARC_D.
Host Bus Acknowledge.
(Common to all SHARCs)
The AD14160/AD14160L deasserts REDY (low)
to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain
output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP-
21060s to be active drive (A/D). REDY will only be output if the CS and
HBR
inputs are asserted.
Multiprocessing Bus Requests.
(Common to all SHARCs)
Used by multiprocessing ADSP-2106xs to
arbitrate for bus mastership. An ADSP-2106x only drives its own
BR
x line (corresponding to the value of
its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the
unused
BR
x pins should be pulled high;
BR
4-1
must not be pulled high or low because they are outputs.
Multiprocessing ID.
(Individual ID2–0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D.)
Determines which multiprocessing bus request (
BR1
–
BR6
) is used by individual ADSP-2106x’s. ID =
001 corresponds to
BR1
, ID = 010 corresponds to
BR2
, etc. ID = 000 is reserved for single processor
systems. These lines are a system configuration selection, which should be hardwired or only changed at
reset.
Rotating Priority Bus Arbitration Select.
(Common to all SHARCs)
When RPBA is high, rotating
priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This
signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the
value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on
every ADSP-2106x.
Core Priority Access.
(y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an
ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus.
CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is
required. The CPA pin of each internal ADSP-21060 is brought out individually. The CPA pin has
an internal 5 k
pull-up resistor. If core access priority is not required in a system, the CPA pin
should be left unconnected.
Data Transmit
(Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). DT
pin has a 50 k
internal pull-up resistor.
Data Receive
(Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). DR pin
has a 50 k
internal pull-up resistor.
Transmit Clock
(Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
TCLK pin has a 50 k
internal pull-up resistor.
Receive Clock
(Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). RCLK
pin has a 50 k
internal pull-up resistor.
Transmit Frame Sync
(Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
Receive Frame Sync
(Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
HBR
I/A
HBG
I/O
CSA
CSB
CSC
CSD
REDY (O/D)
I/A
I/A
I/A
I/A
O
BR
6-1
I/O/S
IDy2-0
I
RPBA
I/S
CPA
y (O/D)
I/O
DTy0
O/T
DRy0
I
TCLKy0
I/O
RCLKy0
I/O
TFSy0
RFSy0
I/O
I/O
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