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參數資料
| 型號： | AD14160LKB-4 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | Quad-SHARC DSP Multiprocessor Family |
| 中文描述： | 48-BIT, 40 MHz, OTHER DSP, CBGA452 |
| 封裝： | CERAMIC, BGA-452 |
| 文件頁數： | 23/52頁 |
| 文件大小： | 1193K |
| 代理商： | AD14160LKB-4 |
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AD14160/AD14160L
–23–
REV. A
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
Timing Requirements:
t
HBGRCSV
t
SHBRI
t
HHBRI
t
SHBGI
t
HHBGI
t
SBRI
t
HBRI
t
SRPBAI
t
HRPBAI
HBG
Low to
RD
/
WR
/
CS
Valid
1
HBR
Setup Before CLKIN
2
HBR
Hold Before CLKIN
2
HBG
Setup Before CLKIN
HBG
Hold Before CLKIN High
BR
x,
CPA
Setup Before CLKIN
3
BR
x,
CPA
Hold Before CLKIN High
RPBA Setup Before CLKIN
RPBA Hold Before CLKIN
19.5 + 5DT/4
19.5 + 5DT/4
ns
ns
ns
ns
ns
ns
ns
ns
ns
20 + 3DT/4
20 + 3DT/4
14 + 3DT/4
14 + 3DT/4
13 + DT/2
13 + DT/2
6 + DT/2
6 + DT/2
13.5 + DT/2
13.5 + DT/2
6 + DT/2
6 + DT/2
21.5 + 3DT/4
21.5 + 3DT/4
12 + 3DT/4
12 + 3DT/4
Switching Characteristics:
t
DHBGO
t
HHBGO
t
DBRO
t
HBRO
t
DCPAO
t
TRCPA
t
DRDYCS
HBG
Delay After CLKIN
HBG
Hold After CLKIN
BR
x Delay After CLKIN
BR
x Hold After CLKIN
CPA
Low Delay After CLKIN
CPA
Disable After CLKIN
REDY (O/D) or (A/D) Low from
CS
and
HBR
Low
4
REDY (O/D) Disable or REDY (A/D)
High from
HBG
4
REDY (A/D) Disable from
CS
or
HBR
High
4
7.5 – DT/8
7.5 – DT/8
ns
ns
ns
ns
ns
ns
–2 – DT/8
–2 – DT/8
8 – DT/8
8 – DT/8
–2 – DT/8
–2 – DT/8
8.5 – DT/8
5 – DT/8
8.5 – DT/8
5 – DT/8
–2 – DT/8
–2 – DT/8
9.5
10.25
ns
t
TRDYHG
43.5 + 27DT/16
43.5 + 27DT/16
ns
t
ARDYTR
11
11
ns
NOTES
1
For first asynchronous access after
HBR
and
CS
asserted, ADDR
31–0
must be a non-MMS value 1/2 t
CK
before
RD
or
WR
goes low or by t
HBGRCSV
after HBG goes
low. This is easily accomplished by driving an upper address signal high when
HBG
is asserted.
2
Only required for recognition in the current cycle.
3
CPA
assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
(O/D) = open drain, (A/D) = active drive.
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106x’s (
BR
x) or a host processor
(
HBR
,
HBG
).
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