參數(shù)資料
型號： AD14160LKB-4
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Quad-SHARC DSP Multiprocessor Family
中文描述： 48-BIT, 40 MHz, OTHER DSP, CBGA452
封裝： CERAMIC, BGA-452
文件頁數(shù)： 16/52頁
文件大小： 1193K
代理商： AD14160LKB-4
AD14160/AD14160L
–16–
REV. A
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
Clock Input
Timing Requirements:
t
CK
t
CKL
t
CKH
t
CKRF
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V–2.0 V)
25
7
5
100
25
8.75
5
100
ns
ns
ns
ns
3
3
CLKIN
t
CKH
t
CK
t
CKL
Figure 9. Clock Input
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
Reset
Timing Requirements:
t
WRST
t
SRST
RESET
Pulsewidth Low
1
RESET
Setup Before CLKIN High
2
4t
CK
14.5 + DT/2
4t
CK
14.5 + DT/2
ns
ns
t
CK
t
CK
NOTES
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while
RESET
is
low, assuming stable V
and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after
reset.
CLKIN
RESET
t
WRST
t
SRST
Figure 10. Reset
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
Interrupts
Timing Requirements:
t
SIR
t
HIR
t
IPW
IRQ
2-0
Setup Before CLKIN High
1
IRQ
2-0
Hold Before CLKIN High
1
IRQ
2-0
Pulsewidth
2
18 + 3DT/4
18 + 3DT/4
ns
ns
ns
12 + 3DT/4
12 + 3DT/4
2 + t
CK
2 + t
CK
NOTES
1
Only required for
IRQx
recognition in the following cycle.
2
Applies only if t
SIR
and t
HIR
requirements are not met.
CLKIN
IRQ
2-0
t
IPW
t
SIR
t
HIR
Figure 11. Interrupts
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