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參數(shù)資料
| 型號： | AB28F400BX-T90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | JT 32C 32#20 PIN RECP |
| 中文描述： | 256K X 16 FLASH 12V PROM, 90 ns, PDSO44 |
| 封裝： | 1.110 X 0.525 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 32/34頁 |
| 文件大?。?/td> | 461K |
| 代理商： | AB28F400BX-T90 |
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A28F400BX-T/B
AC CHARACTERISTICSDCE
Y
-CONTROLLED WRITE OPERATIONS
(1, 9)
Versions
A28F400BX-90
(10)
Unit
Symbol
Parameter
Notes
Min
Max
t
AVAV
t
PHEL
t
WLEL
t
PHHEH
t
VPEH
t
AVEH
t
DVEH
t
ELEH
t
EHDX
t
EHAX
t
EHWH
t
EHEL
t
EHQV1
t
WC
t
PS
t
WS
t
PHS
t
VPS
t
AS
t
DS
t
CP
t
DH
t
AH
t
WH
t
CPH
Write Cycle Time
90
ns
RP
Y
High Recovery to CE
Y
Going Low
210
ns
WE
Y
Setup to CE
Y
Going Low
0
ns
RP
Y
V
HH
Setup to CE
Y
Going High
V
PP
Setup to CE
Y
Going High
Address Setup to CE
Y
Going High
6, 8
100
ns
5, 8
100
ns
3
60
ns
Data Setup to CE
Y
Going High
4
60
ns
CE
Y
Pulse Width
60
ns
Data Hold from CE
Y
High
4
0
ns
Address Hold from CE
Y
High
3
10
ns
WE
Y
Hold from CE
Y
High
10
ns
CE
Y
Pulse Width High
30
ns
Duration of Word/Byte Programming
Operation
2, 5
7
m
s
t
EHQV2
t
EHQV3
t
EHQV4
t
QWL
t
QVPH
t
PHBR
Duration of Erase Operation (Boot)
2, 5, 6
0.4
s
Duration of Erase Operation (Parameter)
2, 5
0.4
s
Duration of Erase Operation (Main)
2, 5
0.7
s
t
VPH
t
PHH
V
PP
Hold from Valid SRD
RP
Y
V
HH
Hold from Valid SRD
Boot-Block Relock Delay
5, 8
0
ns
6, 8
0
ns
7
100
ns
NOTES:
1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE
Y
and WE
Y
in systems where
CE
Y
defines the write pulse-width (within a longer WE
Y
timing waveform), all set-up, hold and inactive WE
Y
times should
be measured relative to the CE
Y
waveform.
2, 3, 4, 5, 6, 7, 8: Refer to AC Characteristics for WE
Y
-Controlled Write Operations.
9. Read timing characteristics during write and erase operations are the same as during read-only operations. Refer to AC
Characteristics during Read Mode.
10. See Standard Test Configuration.
32
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