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參數資料
| 型號： | AB28F400BX-T90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | JT 32C 32#20 PIN RECP |
| 中文描述： | 256K X 16 FLASH 12V PROM, 90 ns, PDSO44 |
| 封裝： | 1.110 X 0.525 INCH, PLASTIC, SOP-44 |
| 文件頁數： | 11/34頁 |
| 文件大小： | 461K |
| 代理商： | AB28F400BX-T90 |
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A28F400BX-T/B
Table 1. Bus Operations for WORD-WIDE Mode (BYTE
Y
e
V
IH
)
Mode
Notes
RP
Y
CE
Y
OE
Y
WE
Y
A
9
A
0
V
PP
DQ
0–15
Read
1, 2, 3
V
IH
V
IL
V
IL
V
IH
X
X
X
D
OUT
Output Disable
V
IH
V
IL
V
IH
V
IH
X
X
X
High Z
Standby
V
IH
V
IH
X
X
X
X
X
High Z
Deep Power-Down
9
V
IL
X
X
X
X
X
X
High Z
Intelligent Identifier (Mfr)
4
V
IH
V
IL
V
IL
V
IH
V
ID
V
IL
X
0089H
Intelligent Identifier (Device)
4, 5
V
IH
V
IL
V
IL
V
IH
V
ID
V
IH
X
4470H
4471H
Write
6, 7, 8
V
IH
V
IL
V
IH
V
IL
X
X
X
D
IN
Table 2. Bus Operations for BYTE-WIDE Mode (BYTE
e
V
IL
)
RP
Y
CE
Y
OE
Y
Mode
Notes
WE
Y
A
9
A
0
A
b
1
V
PP
DQ
0–7
DQ
8–14
Read
1, 2, 3
V
IH
V
IL
V
IL
V
IH
X
X
X
X
D
OUT
High Z
Output Disable
V
IH
V
IL
V
IH
V
IH
X
X
X
X
High Z
High Z
Standby
V
IH
V
IH
X
X
X
X
X
X
High Z
High Z
Deep Power-Down
9
V
IL
X
X
X
X
X
X
X
High Z
High Z
Intelligent
Identifier (Mfr)
4
V
IH
V
IL
V
IL
V
IH
V
ID
V
IL
X
X
89H
High Z
Intelligent
Identifier (Device)
4, 5
V
IH
V
IL
V
IL
V
IH
V
ID
V
IH
X
X
70H
71H
High Z
Write
6, 7, 8
V
IH
V
IL
V
IH
V
IL
X
X
X
X
D
IN
High Z
NOTES:
1. Refer to DC Characteristics.
2. X can be V
IL
, V
IH
for control pins and addresses, V
PPL
or V
PPH
for V
PP
.
3. See DC Characteristics for V
PPL
, V
PPH
, V
HH
, V
ID
voltages.
4. Manufacturer and Device codes may also be accessed via a CUI write sequence. A
1
–A
17
e
X.
5. Device ID
e
4470H for A28F400BX-T and 4471H for A28F400BX-B.
6. Refer to Table 3 for valid D
IN
during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when V
PP
e
V
PPH
.
8. To write or erase the boot block, hold RP
Y
at V
HH
.
9. RP
Y
must be at GND
g
0.2V to meet the 80
m
A maximum deep power-down current.
3.2 Read Operations
The 4-Mbit boot block flash family has three user
read modes; Array, Intelligent Identifier, and Status
Register. Status Register read mode will be dis-
cussed in detail in the ‘‘Write Operations’’ section.
During power-up conditions (V
CC
supply ramping), it
takes a maximum of 300 ns from when V
CC
is at
4.5V minimum to valid data on the outputs.
3.2.1 READ ARRAY
If the memory is not in the Read Array mode, it is
necessary to write the appropriate read mode com-
mand to the CUI. The 4-Mbit boot block flash family
has three control functions, all of which must be logi-
cally active, to obtain data at the outputs. Chip-En-
able CE
Y
is the device selection control. Reset/
Power-Down, RP
Y
is the device power control. Out-
put-Enable OE
Y
is the DATA INPUT/OUTPUT
(DQ
[
0:15
]
or DQ
[
0:7
]
) direction control and when
active is used to drive data from the selected memo-
ry on to the I/O bus.
11
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