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參數(shù)資料
| 型號： | AB28F400BX-T90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | JT 32C 32#20 PIN RECP |
| 中文描述： | 256K X 16 FLASH 12V PROM, 90 ns, PDSO44 |
| 封裝： | 1.110 X 0.525 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 20/34頁 |
| 文件大小： | 461K |
| 代理商： | AB28F400BX-T90 |
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A28F400BX-T/B
290501–9
Bus
Command
Comments
Operation
Write
Setup
Erase
Data
e
20H
Address
e
Within block to be
erased
Write
Erase
Data
e
D0H
Address
e
Within block to be
erased
Read
Status Register Data.
Toggle OE
Y
or CE
Y
to update
Status Register
Standby
Check SR.7
1
e
Ready, 0
e
Busy
Repeat for subsequent blocks.
Full status check can be done after each block or after a
sequence of blocks.
Write FFH after the last block erase operation to reset the
device to Read Array Mode.
Full Status Check Procedure
290501–10
Bus
Command
Comments
Operation
Standby
Check SR.3
1
e
V
PP
Low Detect
Standby
Check SR.4,5
Both 1
e
Command Sequence
Error
Standby
Check SR.5
1
e
Block Erase Error
SR.3 MUST be cleared, if set during an erase attempt,
before further attempts are allowed by the Write State
Machine.
SR.5 is only cleared by the Clear Status Register
Command, in cases where multiple blocks are erased
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 8. Automated Block Erase Flowchart
20
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