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參數(shù)資料
| 型號(hào)： | AB28F400BX-T90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | JT 32C 32#20 PIN RECP |
| 中文描述： | 256K X 16 FLASH 12V PROM, 90 ns, PDSO44 |
| 封裝： | 1.110 X 0.525 INCH, PLASTIC, SOP-44 |
| 文件頁(yè)數(shù)： | 18/34頁(yè) |
| 文件大?。?/td> | 461K |
| 代理商： | AB28F400BX-T90 |
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A28F400BX-T/B
290501–5
Bus
Command
Comments
Operation
Write
Setup
Program
Data
e
40H
Address
e
Byte to be
programmed
Write
Program
Data to be programmed
Address
e
Byte to be
programmed
Read
Status Register Data.
Toggle OE
Y
or CE
Y
to update
Status Register
Standby
Check SR.7
1
e
Ready, 0
e
Busy
Repeat for subsequent bytes.
Full status check can be done after each byte or after a
sequence of bytes.
Write FFH after the last byte programming operation to
reset the device to Read Array Mode.
Full Status Check Procedure
290501–6
Bus
Command
Comments
Operation
Standby
Check SR.3
1
e
V
PP
Low Detect
Standby
Check SR.4
1
e
Byte Program Error
SR.3 MUST be cleared, if set during a program attempt,
before further attempts are allowed by the Write State
Machine.
SR.4 is only cleared by the Clear Status Register
Command, in cases where multiple bytes are programmed
before full status is checked.
If error is detected, clear the Status Register before
attempting retry or other error recovery.
Figure 6. Automated Byte Programming Flowchart
18
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