- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378265 > AB28F400BX-T90 (INTEL CORP) JT 32C 32#20 PIN RECP PDF資料下載
參數(shù)資料
| 型號： | AB28F400BX-T90 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | JT 32C 32#20 PIN RECP |
| 中文描述： | 256K X 16 FLASH 12V PROM, 90 ns, PDSO44 |
| 封裝： | 1.110 X 0.525 INCH, PLASTIC, SOP-44 |
| 文件頁數(shù)： | 21/34頁 |
| 文件大?。?/td> | 461K |
| 代理商： | AB28F400BX-T90 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
A28F400BX-T/B
290501–11
Bus
Command
Comments
Operation
Write
Erase
Suspend
Data
e
B0H
Read
Status Register Data.
Toggle OE
Y
or CE
Y
to
update Status Register
Standby
Check SR.7
1
e
Ready
Standby
Check SR.6
1
e
Suspended
Write
Read Array
Data
e
FFH
Read
Read array data from block
other than that being
erased.
Write
Erase Resume
Data
e
D0H
Figure 9. Erase Suspend/Resume Flowchart
3.4 Power Consumption
3.4.1 ACTIVE POWER
With CE
Y
at a logic-low level and RP
Y
at a logic-
high level, the device is placed in the active mode.
The device I
CC
current is a maximum 65 mA at
10 MHz with TTL input signals.
3.4.2 AUTOMATIC POWER SAVINGS
Automatic Power Savings (APS) is a low pwer fea-
ture during active mode of operation. The 4-Mbit
family of products incorporate Power Reduction
Control (PRC) circuitry which basically allows the de-
vice to put itself into a low current state when it is
not being accessed. After data is read from the
memory array, PRC logic controls the device’s pow-
er consumption by entering the APS mode where
maximum I
CC
current is 3 mA and typical I
CC
current
is 1 mA. The device stays in this static state with
outputs valid until a new location is read.
3.4.3 STANDBY POWER
With CE
Y
at a logic-high level (V
IH
), and the CUI in
read mode, the memory is placed in standby mode
where the maximum I
CC
standby current is 100
m
A
with CMOS input signals. The standby operation dis-
ables much of the device’s circuitry and substantially
reduces device power consumption. The outputs
(DQ
[
0:15
]
or DQ
[
0:7
]
) are placed in a high-imped-
ance state independent of the status of the OE
Y
signal. When the 4-Mbit boot block flash family is
deselected during erase or program functions, the
devices will continue to perform the erase or pro-
gram function and consume program or erase active
power until program or erase is completed.
21
相關PDF資料 |
PDF描述 |
|---|---|
| ABR-42018 | Capacitor Selection for the ML6428-1 S-Video Filter |
| ABR-42022 | GT 6C 2#0 4#4 PIN PLUG RTAN |
| AC244 | Octal Buffer/Line Driver with 3-State Outputs |
| ACT244 | Octal Buffer/Line Driver with 3-State Outputs |
| AC74HC40105AP | CMOS DIGITAL INTEGRATED CIRCUIT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AB28F800B5B80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 VOLT BOOT BLOCK FLASH MEMORY |
| AB28F800B5B90 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 VOLT BOOT BLOCK FLASH MEMORY |
| AB28F800B5T80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 VOLT BOOT BLOCK FLASH MEMORY |
| AB28F800B5T90 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:5 VOLT BOOT BLOCK FLASH MEMORY |
| AB28L72K8BFB0S | 制造商:ATP Electronics Inc 功能描述:1GB DDR266 REGISTERED ECC MODULE ULTRA-LOW - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。