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| 型號： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大小： | 281K |
| 代理商： | A6850 |
86
Altera Corporation
a6850 Asynchronous Communications Interface Adapter Data Sheet
Transmitter Control
Bits 5 and 6 of the control register are the
tc
bits, (see
Table 5
). The
tc
bits
are responsible for:
I
Enabling or disabling the interrupt caused by a transmitter data
register empty (
tdre
) condition.
Controlling the request to send (
nrts
) signal.
Transmitting a break character on the
txdata
output.
I
I
Receive Interrupt Enable
Bit 7 of the control register is the
rie
bit. When the
rie
bit is high, the
rdrf
,
ndcd
, and
ovr
bits will assert the
nirq
output. When the
rie
bit is
low,
nirq
generation is disabled.
Status Register
The status register contains the status bits shown in
Table 6
.
Table 5. Transmitter Control Bits
tc1
tc0
nrts
Transmit
Interrupt
Break
Character
0
0
1
1
0
1
0
1
Low
Low
High
Low
Disabled
Enabled
Disabled
Disabled
No
No
No
Yes
Table 6. Status Register Bits
Data Bit
Bit Name
0
1
2
3
4
5
6
7
Receive data register full (
rdrf
)
Transmit data register empty (
tdre
)
Data carrier detect (
ndcd
)
Clear to send (
ncts
)
Framing error (
fe
)
Receiver overrun (
ovr
)
Parity error (
pe
)
Interrupt request (
irq
)
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