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參數(shù)資料
| 型號(hào)： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 281K |
| 代理商： | A6850 |
Altera Corporation
81
a6850
Asynchronous Communications
Interface Adapter
September 1996, ver. 1
Data Sheet
A-DS-A6850-01
Features
I
a6850
communications interface adapter (ACIA)
Optimized for FLEX
Programmable word lengths, stop bits, and parity
Offers divide-by-1, -16, or -64 mode
Includes error detection
Uses approximately 237 FLEX logic elements (LEs)
Functionally based on the Motorola MC6850 device, except as noted
in the
“Variations & Clarifications” section on page 94
MegaCore function implementing an asychronous
I
I
I
I
I
I
and MAX
architectures
General
Description
The
asynchronous receiver/transmitter (UART). The
interface between a microprocessor and a serial communications channel.
The
a6850
receives and transmits data in a variety of configurations,
including 7- or 8-bit data words, with odd, even, or no parity, and 1 or 2
stop bits. See
Figure 1
.
a6850
MegaCore function implements an ACIA, which is a universal
a6850
provides an
Figure 1. a6850 Symbol
A6850
nIRQ
nRTS
TXDATA
DO[7..0]
nCTS
nDCD
E
nRESET
RS
RnW
RXCLK
RXDATA
TXCLK
CS[2..0]
DI[7..0]
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