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參數(shù)資料
| 型號： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 281K |
| 代理商： | A6850 |
Altera Corporation
93
a6850 Asynchronous Communications Interface Adapter Data Sheet
Transmit Start Bit
After data is transferred to the output shift register, a start bit (i.e., logic
low) is placed on the
txdata
output on the falling edge of
txclk
. The start
bit stays active for the number of clock cycles specified by the divide-by
mode (i.e., 1, 16, or 64).
Transmit Data
After the start bit, the data bits shift out of the register one at a time, from
the least significant to the most significant. The cycle time for each bit
starts at the beginning of the specified clock cycle (i.e., -1, -16, or -64). The
number of bits shifted out corresponds to the number of bits specified in
the control register.
Transmit Parity Bit
If parity is enabled, the bit following the last data bit is a parity bit. The
parity bit has a value that forces all the data to have the correct parity. For
example, if parity is set to odd in the control register, then the parity bit
guarantees there are an odd number of 1s (i.e., data plus the parity bit). If
parity is set to even in the control register, then the parity bit guarantees
there is an even number of 1s (i.e., data plus the parity bit).
Transmit Stop Bit
After the parity bit is transmitted, or the last data bit if parity is not
enabled, one or two stop bits are transmitted on
txdata
output. The
output then stays high until the beginning of the next data word
transmission.
Interrupt Operation
The
nirq
output is designed to be an interrupt to a microprocessor or
other controlling device. The
nirq
outputs a variety of conditions
including transmit and receive.
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