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參數(shù)資料
| 型號： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 281K |
| 代理商： | A6850 |
90
Altera Corporation
a6850 Asynchronous Communications Interface Adapter Data Sheet
Figure 3. Read & Write Cycle Waveforms
The X indicates “don’t care.”
Receiver Operation
Receiver operation includes the following functions:
I
I
I
I
I
Start bit detection
Data bit sampling
Parity & stop bit detection
Error detection
Receive data register transfer
Start Bit Detection
The
a6850
begins receiving data when a start bit is detected. A start bit is
a logic low over the
rxdata
input, and is sampled on each rising edge of
the
rxclk
signal. Once the
a6850
detects a logic low, it begins counting
the logic low samples according to the specified divide-by mode (i.e., -1,
-16, or -64).
For example, after detecting a logic low in divide-by-1 mode, the
a6850
assumes the next rising edge is data. After detecting a logic low in divide-
by-16 mode, however, the
a6850
counts 8 clock edges and samples again.
The data must still be a logic low. At this point, the
a6850
assumes the
data and clock are synchronized, and samples data every 16 clock edges
thereafter. Divide-by-64 mode is similar to divide-by-16, with the logic
low sampled at the first rising edge and the 32nd rising edge of
rxclk
.
Data is then sampled every 64 rising edges.
Read
Write
rnw
e
cs
rs
di
do
X
X
X
X
X
X
X
X
110
110
Valid
Undefined
Undefined
X
X
X
Valid
Valid
Data input setup
Control signal setup
Control signal setup
Valid
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