- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366307 > A6850 (Altera Corporation) Asynchronous Communications Interface Adapter PDF資料下載
參數(shù)資料
| 型號(hào)： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大小： | 281K |
| 代理商： | A6850 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)
Altera Corporation
85
a6850 Asynchronous Communications Interface Adapter Data Sheet
Word Select
Bits 2, 3, and 4 of the control register are the
ws
bits, which determine the
word length, parity, and number of stop bits. See
Table 4
.
Table 3. Counter Divide Select Bits
cds1
cds0
Function
0
0
Divide-by-1 mode. Clock and data rate are identical. External
logic is responsible for synchronizing
rxdata
to
rxclk
. The
rxdata
signal is sampled on the rising edge of
rxclk
, and
the
txdata
signal is asserted on the falling edge of
txclk
.
Divide-by-16 mode. The clock rate is 16 times the data rate.
After start bit detection (
rxdata
low), the
rxdata
signal is
sampled on the 9th rising edge of
rxclk
. After writing to the
transmitter data register, the
txdata
signal is asserted on
the first falling edge of
txclk
and every 16 clocks thereafter.
Divide-by-64 mode. The clock rate is 64 times the data rate.
After start bit detection (
rxdata
low), the
rxdata
signal is
sampled on the 33rd rising edge of
rxclk
. After writing to the
transmitter data register, the
txdata
signal is asserted on
the first falling edge of
txclk
and every 64 clocks thereafter.
Master reset. When master reset is selected, the
a6850
is
reset to a known state; the status register is cleared, and the
transmit and receive operations are halted and initialized.
0
1
1
0
1
1
Table 4. Word Select Bits
ws2
ws1
ws0
Word
Length
Stop Bits
Parity
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
7
7
7
8
8
8
8
2
2
1
1
2
1
1
1
Even
Odd
Even
Odd
None
None
Even
Odd
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A7040HN-100M | Fixed Inductors for Digital Audio Amplifier |
| A7040HN-120M | Fixed Inductors for Digital Audio Amplifier |
| A7040HN-150M | Fixed Inductors for Digital Audio Amplifier |
| A7040HN-180M | Fixed Inductors for Digital Audio Amplifier |
| A7040HN-220M | Fixed Inductors for Digital Audio Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A6850KLT | 制造商:ALLEGRO 功能描述:Pb Free |
| A6850KL-T | 制造商:Allegro MicroSystems 功能描述:Power Distribution Load Switch IC |
| A6850KLTR-T | 功能描述:IC SWITCH INTERFACE 2CHAN 8-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| A6852S/N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Hall Sensor IC |
| A6-853221 | 制造商:DWYER INSTRUMENTS 功能描述:A6-853221 SS PR SW 91-150 PSI |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。