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| 型號： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 281K |
| 代理商： | A6850 |
92
Altera Corporation
a6850 Asynchronous Communications Interface Adapter Data Sheet
The
a6850
receives data with one or two stop bits. If one stop bit is
specified in the control register, the
a6850
will expect one stop bit before
starting the synchronization process. Similarly, if two stop bits are
specified, the synchronization process begins after detecting two stop bits.
Error Detection
Three errors can occur when receiving: framing, overrun, and parity.
Refer to the status register error definitions on
page 88
of this data sheet
for more information.
Receive Data Register Transfer
Once the last stop bit is received or a framing error is detected, the data in
the input shift register is transferred to the receiver data register. At this
point, all status bits associated with this data word are set, including the
rdrf
bit. If receive interrupt is enabled, an interrupt on
nirq
is generated.
The receive process concludes when the microprocessor reads data from
the receiver data register.
Transmit Operation
The transmit operation includes the following functions:
I
I
I
I
I
Transmit data register write/transfer
Transmit start bit
Transmit data
Transmit parity bit
Transmit stop bit
Transmit Data Register Write/Transfer
A transmit operation starts when the microprocessor writes data to the
transmitter data register. In the initial write operation, if the output shift
register is empty, data is immediately transferred and the shift operation
begins. However, if a shift operation is underway, the data is held in the
transmitter data register until the active shift operation is finished.
When data is in the transmitter data register, the
tdre
signal is cleared.
Once the data is transferred to the output shift register, the
tdre
status bit
is set. At this point, if transmit interrupt is enabled, an interrupt on
nirq
is generated.
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