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參數(shù)資料
| 型號(hào)： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 281K |
| 代理商： | A6850 |
82
Altera Corporation
a6850 Asynchronous Communications Interface Adapter Data Sheet
Table 1
describes the input and output ports of the
a6850
.
Table 1. a6850 Ports
Name
Type
Polarity
Description
ncts
Input
Low
Clear to send, a modem signal name. The
assertion of the transmit data register empty (
Data carrier detect, a modem signal name. When the
transitions from low to high, an interrupt to the microprocessor is
generated.
Enable for the microprocessor interface. When
microprocessor can access the registers.
Asynchronous reset for the registers and control logic. The
pin was not included in the original MC6850 device.
Register select. This input selects the register based on
is high (signaling a read operation), then
data register and
rs
= 0 selects the status register. However, if
is low (signaling a write operation), then
transmitter data register and
rs
= 0 selects the control register.
Read/write register controls. When
reads the registers; when
rnw
is low, the microprocessor writes to
the registers.
Receive clock. The receive control register samples
on
rxclk
and the state of the counter divide select (
control register.
Receive data. Serial data input from the modem or peripheral.
Transmit clock. Data is asserted to
txclk
.
Chip select from the microprocessor. Chip selec
state for the
a6850
to be selected.
Parallel data input from the microprocessor or other controlling
device.
Interrupt request to microprocessor.
Request to send. Bits 5 and 6 (transmitter control bits) of the control
register set the
nrts
bit. The
nrts
low, or bits 5 and 6 are both high.
Transmit data. Serial output to the modem or peripheral.
Parallel data output to the microprocessor or other controlling device.
ncts
input inhibits the
tdre
) status bit.
ndcd
Input
Low
ndcd
signal
e
Input
High
e
is high, the
nreset
Input
Low
nreset
rs
Input
–
rnw
. If
rnw
rs
= 1 selects the receiver
rnw
rs
= 1 selects the
rnw
Input
Low
rnw
is high, the microprocessor
rxclk
Input
–
rxdata
cds
) bits in the
based
rxdata
Input
Input
–
–
txclk
txdata
on the falling edge of
cs[2..0]
Input
–
t
must be in the
110
di[7..0]
Input
–
nirq
Output
Output
Low
Low
nrts
signal is asserted when bit 6 is
txdata
Output
Output
–
–
do[7..0]
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