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| 型號： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 281K |
| 代理商： | A6850 |
Altera Corporation
91
a6850 Asynchronous Communications Interface Adapter Data Sheet
Data Bit Sampling
After detecting a logic low, the
a6850
samples and shifts the data into the
input shift register. Data bit sampling occurs on every rising edge in
divide-by-1 mode, every 16 rising edges in divide-by-16 mode, and every
64 rising edges in divide-by-64 mode. Each time a bit is sampled, parity is
calculated for future error detection. See
Figure 4
.
Figure 4. a6850 Receiver Functional Waveforms
Parity & Stop Bit Detection
The
a6850
counts the number of data bits as it shifts. When the number of
data bits received matches the number specified in the control register, the
a6850
expects either a parity bit or a stop bit.
If parity is enabled, the
a6850
samples for the parity bit, which is then
processed for parity. However, if parity is not enabled, the
a6850
samples
for a stop bit (i.e., logic high). If a logic low is sampled, the
fe
bit is set in
the status register.
Divide-by-1 Mode
Divide-by-16 Mode
txdata
rxdata
Sampled on rising edge of rxclk
txdata
Driven from falling edge of txclk
rxclk
or txclk
rxdata
Sampling Pulse
Start Bit
Data Bit
Start Bit
Data Bit
rxclk
txclk
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