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參數資料
| 型號： | A6850 |
| 廠商： | Altera Corporation |
| 英文描述： | Asynchronous Communications Interface Adapter |
| 中文描述： | 異步通信接口適配器 |
| 文件頁數： | 4/15頁 |
| 文件大小： | 281K |
| 代理商： | A6850 |
84
Altera Corporation
a6850 Asynchronous Communications Interface Adapter Data Sheet
Transmitter Data Register
The transmitter data register (TDR) is written to by the microprocessor or
other controlling device. Once the existing data bits in the output shift
register are completely transmitted out, the TDR transfers new data into
the output shift register.
Receiver Data Register
The receiver data register (RDR) is written to by the input shift register.
Once the existing data in the RDR is read, the input shift register transfers
new data into the RDR. If 7-bit data is selected, bit 7 is set to a logic low.
Control Register
The control register contains the control bits shown in
Table 2
.
Counter Divide Select
Bits 0 and 1 of the control register are the
ratio between the data rate and the clocks. The ratios when transmitting
and receiving are identical. The
cds
bits can also be used to reset the
a6850
to a known state. See
Table 3
.
cds
bits, which determine the
Table 2. Control Register Bits
Data Bit
Signal Name
0
1
2
3
4
5
6
7
Counter divide select 0 (
Counter divide select 1 (
Word select 0 (
Word select 1 (
Word select 2 (
Transmitter control 0 (
Transmitter control 1 (
Receive interrupt enable (
cds0
)
)
cds1
ws0
)
)
)
ws1
ws2
tc0
)
)
rie
)
tc1
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