參數(shù)資料
型號(hào)： 935268252557
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁(yè)數(shù)： 64/80頁(yè)
文件大?。?/td> 306K
代理商： 935268252557
Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
64
13.4
Indirect Address Registers
13.4.1
The host interface register set has been extended to provide additional control and data registers for FIFO size control and copy protection
control registers. These extensions have been implemented via an indirect addressing mechanism. This mechanism allows software written for
previous versions of the AV Link (PDI1394L21 and PDI1394L11) to operate on the PDI1394L40 with minimal changes.
To read or write from the indirect memory, you first write the appropriate address into the indirect address register (A8 = 1), then read or write
from (or to) the indirect data increment the indirect address by one quadlet. Therefore, if you are writing several quadlets to continuous
addresses, you will not need to increment the indirect address register.
13.4.2
Indirect Address Register (INDADDR) – Base Address: 0x0F8
SV01027
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
INDADDR
RESERVED
Bit 15..0:
R/W
Indirect Address: To read or write from the indirect memory, you first write the appropriate address into the indirect
address register (A8 = 1), then read or write from (or to) the indirect data register (INDDATA, 0x0FC). Each write or
read (A8 = 1) to the indirect data register (INDDATA) will automatically increment the indirect address by one
quadlet. The following addresses are defined in the indirect address space:
Table 8.
INDADDR address and function
INDADDR
FUNCTION
0–0x0FC
Reserved
0x100–0x1FC
FIFO Size Registers
0x500–0xFFFF
Reserved
13.4.3
Indirect Data Register (INDDATA) – Base Address: 0x0FC
SV01764
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
0
WINDOW TO THE INDIRECT QUADLET POINTED TO BY INDADDR
Bit 31..0:
R/W
Quadlet of data pointed to by the indirect address n the INDADDR register (0x0F8). Note that the Indirect address
autoincrements on each read or write of the INDDATA register.
相關(guān)PDF資料
PDF描述
08008GOB 125 A, 800 V, SCR, TO-209AC
935268252551 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
08008GOC 125 A, 800 V, SCR, TO-209AC
08008GOD 125 A, 800 V, SCR, TO-208AD
08010GOB 125 A, 1000 V, SCR, TO-209AC
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