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參數(shù)資料
| 型號： | 935268252557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 48/80頁 |
| 文件大?。?/td> | 306K |
| 代理商： | 935268252557 |
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Philips Semiconductors
Preliminary specification
PDI1394L40
1394 enhanced AV link layer controller
2000 Dec 15
49
13.1.6
Phy Register Access (PHYACS) – Base Address: 0x014
This register provides access to the internal registers on the Phy. There are special considerations when reading or writing to this register. When
reading a PHY register, the address of the register is written to the PHYRGAD field with the RDPHY bit set. The PHY data will be valid when the
PHYRRX bit (LNKPHYINTACK register bit 14) is set. Once this happens the register data is available in the PHYRXDATA, the address of the
register just read is also available in the PHYRXAD fields. When writing a Phy register, the address of the register to be written is set in the
PHYRGAD field and the data to be written to the register is set in PHYRGDATA, along with the WRPHY bit being set. Once the write is
complete, the WRPHY bit will be cleared. Do not write a new Read/Write command until the previous one has been completed. After the Self-ID
phase, PHY register 0 will be read automatically.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDPHY
WRPHY
SV00277
PHYRGAD
PHYRGDATA
PHYRXAD
PHYRXDATA
31 30
Reset Value 0x00000000
Bit 31:
R/W
Read Phy Chip Register (RDPHY): When asserted, the PDI1394L40 sends a read register request with address
equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.
Bit 30:
R/W
Write Phy Chip Register (WRPHY): When asserted, the PDI1394L40 sends a write register request with address
equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent.
Bit 27..24:
R/W
Phy Chip Register Address (PHYRGAD): This is the address of the Phy-chip register that is to be accessed.
Bit 23..16:
R/W
Phy Chip Register Data (PHYRGDATA): This is the data to be written to the Phy-chip register indicated in Phy Rg Ad.
Bit 11..8:
R
Phy Chip Register Received Address (PHYRXAD): Address of register from which Phy Rx Data came.
Bit 7..0:
R
Phy Chip Register Received Data (PHYRXDATA): Data from register addressed by Phy Rx Ad.
13.1.7
Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018
This register is the top level interrupt status register. If the external interrupt line is set, this register will indicate which major portion of the AV
Link generated the interrupt. There is no interrupt acknowledge required at this level. These bits auto clear when the interrupts in the
appropriate section of the device are cleared or disabled. Control of the AV transceiver is also provided by this register.
Bits 0 to 3 are used to identify which internal modules are currently generating an interrupt. After identifying the module, the appropriate register
in that module must be read to determine the exact cause of the interrupt.
A timer is available to aid the implementation of higher level protocols such as AV/C and HAVi. The timer can be started and stopped, and
automatically reloads with 1s (TIMLOAD = 1) or 100ms (TIMLOAD = 0). When the set time has expired, an interrupt will be generated through
TIMER (Bit 20, LNKPHYINTACK 0x008). In normal timer mode (TIMMODE = 0), the timer will generate an interrupt, reload and restart every
time it expires, until TIMRNSTP is cleared. In bus reset timer mode (TIMMODE = 1), even when already running the timer will reload with 1s
and restart automatically after a bus reset. If another bus reset occurs before the timer expires, the timer will again reload and restart. No
interrupt will be generated until the timer expires.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ASYTX/RX
ITXINT
IRXINT
LNKPHYINT
31 30
EASYTX/RX
EITXINT
EIRXINT
ELNKPHYINT
DIRA
V1
ENOUT
A
V
2
ENOUT
A
V
1
SV01024
NOTES
1. There can be more than one interrupt source active at the same time.
2. The HIF INT_N signal (pin 28) remains active as long as there is at least one more enabled active interrupt status bit.
Reset Value 0x00010000
Bit 18:
R/W
Enable output AVPORT2: A ‘1’ enables AVPORT2 as an output. A ‘0’ sets the 3-State condition on the port. In
3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).
Bit 17:
R/W
Enable output AVPORT1: A ‘1’ enables AVPORT1 as an output. A ‘0’ sets the 3-State condition on the port. In
3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).
相關(guān)PDF資料 |
PDF描述 |
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| 08008GOB | 125 A, 800 V, SCR, TO-209AC |
| 935268252551 | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 08008GOC | 125 A, 800 V, SCR, TO-209AC |
| 08008GOD | 125 A, 800 V, SCR, TO-208AD |
| 08010GOB | 125 A, 1000 V, SCR, TO-209AC |
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